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preliminary information amd athlon xp processor model 8 data sheet publication # 25175 rev. e issue date: november 2002 tm
preliminary information trademarks amd, the amd arrow logo, amd athlon, amd duron, and combinations thereof, quantispeed, and 3dnow! are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. mmx is a trademark of intel corporation. windows is a registered trademark of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2001, 2002 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or war- ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and prod- uct descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
table of contents iii 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 quantispeed? architecture summary. . . . . . . . . . . . . . . . . . . 2 2 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 signaling technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 push-pull (pp) drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 amd athlon? system bus signals . . . . . . . . . . . . . . . . . . . . . . 6 3 logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 working state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 stop grant states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 probe state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 connect and disconnect protocol . . . . . . . . . . . . . . . . . . . . . . 12 connect protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 connect state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 cpuid support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 advanced 266 front-side bus amd athlon xp processor model 8 specifications . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 part-specific electrical and thermal specifications for . . . . . advanced 266 fsb amd athlon xp processors model 8 . . . 21 6.2 advanced 266 fsb amd athlon xp processor model 8 sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . 24 6.3 advanced 266 fsb amd athlon system bus ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 advanced 333 front-side bus amd athlon xp processor model 8 specifications . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 electrical and thermal specifications for the advanced 333 fsb amd athlon xp processor model 8 . . . . . . . . . . . . . . . . 27 7.2 advanced 333 fsb amd athlon xp processor model 8 sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . 28 7.3 advanced 333 fsb amd athlon system bus ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 interface signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
iv table of contents amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.3 voltage identification (vid[4:0]) . . . . . . . . . . . . . . . . . . . . . . 33 8.4 frequency identification (fid[3:0]) . . . . . . . . . . . . . . . . . . . . 33 8.5 vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . 33 8.6 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.7 v cc_core characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.9 sysclk and sysclk# dc characteristics . . . . . . . . . . . . . . 37 8.10 amd athlon system bus dc characteristics . . . . . . . . . . . . . 38 8.11 general ac and dc characteristics . . . . . . . . . . . . . . . . . . . . 39 8.12 open-drain test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.13 thermal diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 thermal diode electrical characteristics. . . . . . . . . . . . . 42 thermal protection characterization . . . . . . . . . . . . . . . . 43 8.14 apic pins ac and dc characteristics . . . . . . . . . . . . . . . . . . 44 9 signal and power-up requirements . . . . . . . . . . . . . . . . . . . . 45 9.1 power-up requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 signal sequence and timing description . . . . . . . . . . . . . 45 clock multiplier selection (fid[3:0]) . . . . . . . . . . . . . . . . 48 9.2 processor warm reset requirements. . . . . . . . . . . . . . . . . . . 48 northbridge reset pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 die loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.3 opga package dimensions of amd athlon xp processors model 8 with a cpuid of 680 . . . . . . . . . . . . . . . . 50 10.4 opga package dimensions of amd athlon xp processors model 8 with a cpuid of 681 . . . . . . . . . . . . . . . . 51 11 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 pin diagram and pin name abbreviations. . . . . . . . . . . . . . . 53 11.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.3 detailed pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 a20m# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 amd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 amd athlon system bus pins . . . . . . . . . . . . . . . . . . . . . . 70 analog pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 apic pins, picclk, picd[1:0]# . . . . . . . . . . . . . . . . . . . . 70 clkfwdrst pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 clkin, rstclk (sysclk) pins. . . . . . . . . . . . . . . . . . . . 70 connect pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 corefb and corefb# pins . . . . . . . . . . . . . . . . . . . . . . . 71 cpu_presence# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 dbrdy and dbreq# pins . . . . . . . . . . . . . . . . . . . . . . . . . 71 ferr pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 fid[3:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 fsb_sense[1:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
table of contents v 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information flush# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ignne# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 init# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 intr pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 k7clkout and k7clkout# pins . . . . . . . . . . . . . . . . . . 74 key pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 nc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 nmi pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 pga orientation pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 pll bypass and test pins . . . . . . . . . . . . . . . . . . . . . . . . . . 74 pwrok pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 saddin[1:0]# and saddout[1:0]# pins . . . . . . . . . . . . . 75 scan pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 smi# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 stpclk# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 sysclk and sysclk#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 thermda and thermdc pins . . . . . . . . . . . . . . . . . . . . 75 vcca pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 vid[4:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 vrefsys pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 zn and zp pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 standard amd athlon xp processor model 8 products . . . . . . . . . . 77 appendix a thermal diode calculations . . . . . . . . . . . . . . . . . . . . . 79 ideal diode equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 temperature offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 appendix b conventions and abbreviations . . . . . . . . . . . . . . . . . . 83 signals and bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 data terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 abbreviations and acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 related publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
vi table of contents amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
list of figures vii 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information list of figures figure 1. typical amd athlon? xp processor model 8 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. amd athlon xp processor model 8 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. amd athlon system bus disconnect sequence in the stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. exiting the stop grant state and bus connect sequence . . . . 15 figure 6. northbridge connect state diagram . . . . . . . . . . . . . . . . . . . . . 16 figure 7. processor connect state diagram . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. v cc_core voltage waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. sysclk and sysclk# differential clock signals . . . . . . . . . 37 figure 12. general ate open-drain test circuit. . . . . . . . . . . . . . . . . . . . 41 figure 13. signal relationship requirements during power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. amd athlon xp processor model 8 opga package . . . . . . . . 52 figure 15. amd athlon xp processor model 8 pin diagram ?topside view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 16. amd athlon xp processor model 8 pin diagram ?bottomside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17. opn example for the amd athlon xp processor model 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
viii list of figures amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
list of tables ix 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information list of tables table 1. electrical and thermal specifications for processors with a cpuid of 680. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2. electrical and thermal specifications for processors with a cpuid of 681. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3. sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . . 24 table 4. amd athlon? system bus ac characteristics . . . . . . . . . . . . 25 table 5. electrical and thermal specifications . . . . . . . . . . . . . . . . . . . . 27 table 6. sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . . 28 table 7. amd athlon system bus ac characteristics . . . . . . . . . . . . . . 29 table 8. interface signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. vid[4:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. fid[3:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. vcc_core ac and dc characteristics . . . . . . . . . . . . . . . . . . 34 table 13. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. sysclk and sysclk# dc characteristics . . . . . . . . . . . . . . . 37 table 15. amd athlon system bus dc characteristics . . . . . . . . . . . . . . 38 table 16. general ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . 39 table 17. thermal diode electrical characteristics . . . . . . . . . . . . . . . . . 42 table 18. guidelines for platform thermal protection of the processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 19. apic pin ac and dc characteristics. . . . . . . . . . . . . . . . . . . . . 44 table 20. mechanical loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21. opga package dimensions for amd athlon xp processors model 8 with a cpuid of 680. . . . . . . . . . . . . . . . . . 50 table 22. opga package dimensions for amd athlon xp processors model 8 with a cpuid of 681. . . . . . . . . . . . . . . . . . 51 table 23. pin name abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. cross-reference by pin location . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. fid[3:0] clock multiplier encodings . . . . . . . . . . . . . . . . . . . . . 72 table 26. front side bus sense truth table . . . . . . . . . . . . . . . . . . . . . . . 73 table 27. vid[4:0] code to voltage definition . . . . . . . . . . . . . . . . . . . . . 76 table 28. constants and variables for the ideal diode equation . . . . . . 79 table 29. constants and variables used in temperature offset equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
x list of tables amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information table 30. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 31. acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
revision history xi 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information revision history date rev description november 2002 e revision e of the amd athlon? xp processor model 8 data sheet includes the following changes: in chapter 6, revised table 2, ?electrical and thermal specifications for processors with a cpuid of 681,? on page 23. in chapter 3, revised figure 2, ?logic symbol diagram,? on page 7. in chapter 7, revised table 5, ?electrical and thermal specifications,? on page 27. in chapter 8, revised table 9, ?vid[4:0] dc characteristics,? on page 33. in chapter 12, revised figure 17, ?opn example for the amd athlon? xp processor model 8,? on page 77. october 2002 d revision d of the amd athlon? xp processor model 8 data sheet includes the following changes: in chapter 1, revised wording in overview. in chapter 6, revised table 2, ?electrical and thermal specifications for processors with a cpuid of 681,? on page 23, added table 3, ?sysclk and sysclk# ac characteristics,? on page 24, figure 8, ?sysclk waveform,? on page 24, and table 4, ?amd athlon? system bus ac characteristics,? on page 25. added chapter 7, ?advanced 333 front-side bus amd athlon? xp processor model 8 specifications? on page 27, table 5, ?electrical and thermal specifications,? on page 27, table 6, ?sysclk and sysclk# ac characteristics,? on page 28, figure 9, ?sysclk waveform,? on page 28, and table 7, ?amd athlon? system bus ac characteristics,? on page 29. in chapter 8, revised table 8, ?interface signal groupings,? on page 31, table 9, ?vid[4:0] dc characteristics,? on page 33, table 10, ?fid[3:0] dc characteristics,? on page 33, and table 19, ?apic pin ac and dc characteristics,? on page 44. in chapter 10, revised table 21, ?opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 680,? on page 50 and table 22, ?opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 681,? on page 51. in chapter 12, revised figure 17, ?opn example for the amd athlon? xp processor model 8,? on page 77.
xii revision history amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information august 2002 c revision c of the amd athlon? xp processor model 8 data sheet includes the following changes: in chapter 3, revised figure 2, ?logic symbol diagram,? on page 7. in chapter 6, added table 1, ?electrical and thermal specifications for processors with a cpuid of 680,? on page 22 and table 2, ?electrical and thermal specifications for processors with a cpuid of 681,? on page 23. in chapter 8, revised table 8, ?interface signal groupings,? on page 31. in chapter 10, added table 21, ?opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 680,? on page 50 and table 22, ?opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 681,? on page 51. in chapter 11, revised figure 15, ?amd athlon? xp processor model 8 pin diagram? topside view,? on page 54, figure 16, ?amd athlon? xp processor model 8 pin diagram? bottomside view,? on page 55, table 23, ?pin name abbreviations,? on page 56, table 24, ?cross-reference by pin location,? on page 64, and added ?fsb_sense[1:0] pins? on page 74, and table 26, ?front side bus sense truth table,? on page 74. in chapter 12, revised figure 17, ?opn example for the amd athlon? xp processor model 8,? on page 77. june 2002 b first release of the amd athlon? xp processor model 8 data sheet date rev description
chapter 1 overview 1 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 1overview the amd athlon? xp processor model 8 with quantispeed? architecture powers the next ge neration in computing platforms, delivering extreme performance for windows ? xp. the amd athlon? xp processor model 8, based on leading- edge 0.13 micron technology, integrates the innovative design and manufacturing expertise of amd to deliver improved performance, lower power, and smaller die size while maintaining the stable and compatible socket a infrastructure of the amd athlon processor. delivered in an opga package, the amd athlon xp processor model 8 delivers the integer, floating-point, and 3d multimedia performance for highly demanding applications running on x86 system platforms. the amd athlon xp processor model 8 delivers compelling performance for cutting-edge software applications that include high-speed internet capability, digital content creation, digital photo editing, digital video, image compression, video encoding for streaming over the internet, soft dvd, commercial 3d modeling, workstation-class computer-aided design (cad), commercial desktop publishing, and speech recognition. the amd athlon xp processor model 8 also offers the scalability and reliability that it managers and business users require for enterprise computing. the amd athlon xp processor model 8 features a seventh-generation microarchitecture with an integrated, exclusive l2 cache, which supports the growing processor and system bandwidth requirements of emerging software, graphics, i/o, and memory technologies. the high-speed execution core of the amd athlon xp processor model 8 includes multiple x86 instruction decoders, a dual-ported 128-kbyte split level-one (l1) cache, an exclusive 256-kbyte l2 cache, three independent integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of-order, three-way floating-point engine. the floating-point engine is capable of deliveri ng outstanding performance on numerically complex applications.
2 overview chapter 1 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information the features of the amd athlon xp processor model 8 are quantispeed? architecture, a high-performance full-speed cache, an advanced 333 front-side bus (fsb) with a 2.7-gigabyte per second system bus, or an advanced 266 fsb with a 2.1-gigabyte per second system bus, and 3dnow!? professional technology. the amd athlon system bus combines the latest technological advances, such as point-to-point topology, source-synchronous packet-based transfers, and low-voltage signaling to provide an extremely powerful, scalable bus for an x86 processor. the amd athlon xp processor model 8 is binary-compatible with existing x86 software and backwards compatible with applications optimized for mmx?, sse, and 3dnow! technology. using a data format and single-instruction multiple-data (simd) operations based on the mmx instruction model, the amd athlon xp processor model 8 can produce as many as four, 32-bit, single-precision floating-point results per clock cycle. the 3dnow! professional technology implemented in the amd athlon xp processor model 8 includes new integer multimedia instructions and software-directed data movement instructions for optimizing such applications as digital content creation and streaming video for the internet, as well as new instructions for digital signal processing (dsp) and communications applications. 1.1 quantispeed? architecture summary the following features summarize the amd athlon xp processor model 8 quantispeed architecture: advanced 333 fsb technology available an advanced nine-issue, superpipelined, superscalar x86 processor microarchitecture designed for increased instructions per cycle (ipc) and high clock frequencies fully pipelined floating-point unit that executes all x87 (floating-point), mmx , sse and 3dnow! instructions hardware data pre-fetch that increases and optimizes performance on high-end software applications utilizing high- bandwidth system capabilities advanced two-level translation look-aside buffer (tlb) structures for both enhanced data and instruction address translation. the amd athlon xp processor model 8 with quantispeed architecture incorporates three tlb optimizations: the l1 dtlb increases from 32 to 40 entries, the l2 itlb and l2 dtlb both use exclusive architecture, and the tlb entries can be speculatively loaded.
chapter 1 overview 3 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information the amd athlon xp processor model 8 delivers excellent system performance in a cost-effective, industry-standard form factor. the amd athlon xp processor model 8 is compatible with motherboards based on socket a. figure 1 shows a typical amd athlon xp processor model 8 system block diagram. figure 1. typical amd athlon? xp processor model 8 system block diagram sdram or ddr agp bus memory bus agp pci bus lan scsi lpc bus usb dual eide amd athlon? xp processor model 8 system controller (northbridge) peripheral bus controller (southbridge) modem / audio thermal monitor bios amd athlon system bus
4 overview chapter 1 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 2 interface signals 5 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 2 interface signals this section describes the interface signals utilized by the amd athlon? xp processor model 8. 2.1 overview the amd athlon? system bus architecture is designed to deliver excellent data movement bandwidth for next- generation x86 platforms as well as the high-performance required by enterprise-class application software. the system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 64-bit bidirectional data channel), source-synchronous clocking, and a packet-based protocol. in addition, the system bus supports several control, clock, and legacy signals. the interface signals use an impedance controlled push-pull, low-voltage, swing-signaling technology contained within the socket a socket. for more information, see ?amd athlon? system bus signals? on page 6, chapter 11, ?pin descriptions? on page 53, and the amd athlon? system bus specification , order# 21902. 2.2 signaling technology the amd athlon system bus uses a low-voltage, swing-signaling technology, that has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. the signals are push-pull and impedance compensated. the signal inputs use differential receivers that require a reference voltage (v ref ). the reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. termination resistors are not needed because the driver is impedance-matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold. for more information about pins and signals, see chapter 11, ?pin descriptions? on page 53.
6 interface signals chapter 2 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 2.3 push-pull (pp) drivers the amd athlon xp processor model 8 supports push-pull (pp) drivers. the system logic configures the processor with the configuration parameter called syspushpull (1=pp). the impedance of the pp drivers is set to match the impedance of the motherboard by two external resistors connected to the zn and zp pins. see ?zn and zp pins? on page 77 for more information. 2.4 amd athlon? system bus signals the amd athlon system bus is a clock-forwarded, point-to- point interface with the following three point-to-point channels: a 13-bit unidirectional output address/command channel a 13-bit unidirectional input address/command channel a 72-bit bidirectional data channel for more information, see chapter 8, ?electrical data? on page 31 and the amd athlon? system bus specification , order# 21902.
chapter 3 logic symbol diagram 7 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 3 logic symbol diagram figure 2 is the logic symbol diagram of the processor. this diagram shows the logical grouping of the input and output signals. figure 2. logic symbol diagram sdata[63:0]# sdatainclk[3:0]# sdataoutclk[3:0]# data saddin[14:2]# saddinclk# probe/syscmd saddout[14:2]# saddoutclk# vid[4:0] fid[3:0] a20m# clkfwdrst connect corefb corefb# ferr ignne# init# intr nmi procrdy pwrok reset# sfillvalid# smi# stpclk# sysclk# sysclk clock voltage control frequency control legacy request amd athlon? xp processor model 8 sdatainvalid# sdataoutvalid# power and management thermal diode thermda thermdc flush# picclk picd[1:0] apic fsb_sense[1:0] { { { { initialization { { { { { front side bus autodetect
8 logic symbol diagram chapter 3 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 4 power management 9 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 4 power management this chapter describes the power management control system of the amd athlon? xp processor model 8. the power management features of the processor are compliant with the acpi 1.0b and acpi 2.0 specifications. 4.1 power management states the amd athlon xp processor model 8 supports low-power halt and stop grant states. these states are used by advanced configuration and power interface (acpi) enabled operating systems for processor power management. figure 3 shows the power management states of the processor. the figure includes the acpi ?cx? naming convention for these states. figure 3. amd athlon? xp processor model 8 power management states c1 halt c0 working 4 execute hlt smi#, intr, nmi, init#, reset# incoming probe p r o b e s e r v i c e d stpclk# asserted s t p c l k # a s s e r t e d 2 s t p c l k # d e a s s e r t e d 3 c2 stop grant cache snoopable incoming probe probe serviced probe state 1 stpclk# deasserted (read plvl2 register or throttling) s1 stop grant cache not snoopable sleep s t p c l k # a s s e r t e d s t p c l k # d e a s s e r t e d note: the amd athlon tm system bus is connected during the following states: 1) the probe state 2) during transitions between the halt state and the c2 stop grant state 3) during transitions between the c2 stop grant state and the halt state 4) c0 working state software transitions hardware transitions legend
10 power management chapter 4 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information the following sections provide an overview of the power management states. for more details, refer to the amd athlon? system bus specification, order# 21902 . note: in all power management states that the processor is powered, the system must not stop the system clock (sysclk/sysclk#) to the processor. working state the working state is the state in which the processor is executing instructions. halt state when the processor executes the hlt instruction, the processor enters the halt state and issues a halt special cycle to the amd athlon system bus. the processor only enters the low power state dictated by the clk_ctl msr if the system controller (northbridge) disconnects the amd athlon system bus in response to the halt special cycle. if stpclk# is asserted, the processor will exit the halt state and enter the stop grant state. the processor will initiate a system bus connect, if it is disconnected, then issue a stop grant special cycle. when stpclk# is deasserted, the processor will exit the stop grant state and re-enter the halt state. the processor will issue a halt special cycle when re-entering the halt state. the halt state is exited when the processor detects the assertion of init#, reset#, smi#, or an interrupt via the intr or nmi pins, or via a local apic interrupt message. when the halt state is exited, the processor will initiate an amd athlon system bus connect if it is disconnected. stop grant states the processor enters the stop grant state upon recognition of assertion of stpclk# input. after entering the stop grant state, the processor issues a stop grant special bus cycle on the amd athlon system bus. the processor is not in a low-power state at this time, because the amd athlon system bus is still connected. after the northbridge disconnects the amd athlon system bus in response to the stop grant special bus cycle, the processor enters a low-power state dictated by the clk_ctl msr. if the northbridge needs to probe the processor during the stop grant state while the system bus is disconnected, it must first connect the system bus. connecting the system bus
chapter 4 power management 11 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information places the processor into the higher power probe state. after the northbridge has completed all probes of the processor, the northbridge must disconnect the amd athlon system bus again so that the processor can return to the low-power state. during the stop grant states, the processor latches init#, intr, nmi, smi#, or a local apic interrupt message, if they are asserted. the stop grant state is exited upon the deassertion of stpclk# or the assertion of reset#. when stpclk# is deasserted, the processor initiates a connect of the amd athlon system bus if it is disconnected. after the processor enters the working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where stpclk# was initially recognized. if reset# is sampled asserted during the stop grant state, the processor exits the stop grant state and the reset process begins. there are two mechanisms for asserting stpclk#?hardware and software. the southbridge can force stpclk# assertion for throttling to protect the processor from exceeding its maximum case temperature. this is accomplished by asserting the therm# input to the southbridge. throttling asserts stpclk# for a percentage of a predefined throttling period: stpclk# is repetitively asserted and deasserted until therm# is deasserted. software can force the processor into the stop grant state by accessing acpi-defined registers typically located in the southbridge. the operating system places the processor into the c2 stop grant state by reading the p_lvl2 register in the southbridge. if an acpi thermal zone is defined for the processor, the operating system can initiate throttling with stpclk# using the acpi defined p_cnt register in the southbridge. the northbridge connects the amd athlon system bus, and the processor enters the probe state to service cache snoops during stop grant for c2 or throttling. in c2, probes are allowed, as shown in figure 3 on page 9
12 power management chapter 4 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information the stop grant state is also entered for the s1, powered on suspend, system sleep state based on a write to the slp_typ and slp_en fields in the acpi-defined power management 1 control register in the southbridge. during the s1 sleep state, system software ensures no bus master or probe activity occurs. the southbridge deasserts stpclk# and brings the processor out of the s1 stop grant state when any enabled resume event occurs. probe state the probe state is entered when the northbridge connects the amd athlon system bus to probe the processor (for example, to snoop the processor caches) when the processor is in the halt or stop grant state. when in the probe state, the processor responds to a probe cycle in the same manner as when it is in the working state. when the probe has been serviced, the processor returns to the same state as when it entered the probe state (halt or stop grant state). when probe activity is completed the processor only returns to a low-power state after the northbridge disconnects the amd athlon system bus again. 4.2 connect and disconnect protocol significant power savings of the processor only occur if the processor is disconnected from the system bus by the northbridge while in the halt or stop grant state. the northbridge can optionally initiate a bus disconnect upon the receipt of a halt or stop grant special cycle. the option of disconnecting is controlled by an enable bit in the northbridge. if the northbridge requires the processor to service a probe after the system bus has been disconnected, it must first initiate a system bus connect. connect protocol in addition to the legacy stpclk# signal and the halt and stop grant special cycles, the amd athlon system bus connect protocol includes the connect, procrdy, and clkfwdrst signals and a connect special cycle. amd athlon system bus disconnects are initiated by the northbridge in response to the re ceipt of a halt or stop grant. reconnect is initiated by the processor in response to an interrupt for halt or stpclk# deassertion. reconnect is initiated by the northbridge to probe the processor.
chapter 4 power management 13 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information the northbridge contains bios programmable registers to enable the system bus disconnect in response to halt and stop grant special cycles. when the northbridge receives the halt or stop grant special cycle from the processor and, if there are no outstanding probes or data movements, the northbridge deasserts connect a minimum of eight sysclk periods after the last command sent to the processor. the processor detects the deassertion of connect on a rising edge of sysclk and deasserts procrdy to the northbridge. in return, the northbridge asserts clkfwdrst in anticipation of reestablishing a connection at some later point. note: the northbridge must disconnect the processor from the amd athlon system bus before issuing the stop grant special cycle to the pci bus or passing the stop grant special cycle to the southbridge for systems that connect to the southbridge with hypertransport? technology. this note applies to current chipset implementation? alternate chipset implementations that do not require this are possible. note: in response to halt special cycles, the northbridge passes the halt special cycle to the pci bus or southbridge immediately. the processor can receive an interrupt after it sends a halt special cycle, or stpclk# deassertion after it sends a stop grant special cycle to the northbridge but before the disconnect actually occurs. in this case, the processor sends the connect special cycle to the northbridge, rather than continuing with the disconnect sequence. in response to the connect special cycle, the northbridge cancels the disconnect request. the system is required to assert the connect signal before returning the c-bit for the connect special cycle (assuming connect has been deasserted). for more information, see the amd athlon? system bus specification , order# 21902 for the definition of the c-bit and the connect special cycle.
14 power management chapter 4 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information figure 4 shows stpclk# assertion resulting in the processor in the stop grant state and the amd athlon system bus disconnected. figure 4. amd athlon? system bus disconnect sequence in the stop grant state an example of the amd athlon system bus disconnect sequence is as follows: 1. the peripheral controller (southbridge) asserts stpclk# to place the processor in the stop grant state. 2. when the processor recognizes stpclk# asserted, it enters the stop grant state and then issues a stop grant special cycle. 3. when the special cycle is received by the northbridge, it deasserts connect, assuming no probes are pending, initiating a bus disconnect to the processor. 4. the processor responds to the northbridge by deasserting procrdy. 5. the northbridge asserts clkfwdrst to complete the bus disconnect sequence. 6. after the processor is disconnected from the bus, the processor enters a low-power state. the northbridge passes the stop grant special cycle along to the southbridge. stop grant stop grant stpclk# connect procrdy clkfwdrst pci bus amd athlon? system bus
chapter 4 power management 15 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information figure 5 shows the signal sequence of events that takes the processor out of the stop grant state, connects the processor to the amd athlon system bus, and puts the processor into the working state. figure 5. exiting the stop grant state and bus connect sequence the following sequence of events removes the processor from the stop grant state and connects it to the system bus: 1. the southbridge deasserts stpclk#, informing the processor of a wake event. 2. when the processor recognizes stpclk# deassertion, it exits the low-power state and asserts procrdy, notifying the northbridge to connect to the bus. 3. the northbridge asserts connect. 4. the northbridge deasserts clkfwdrst, synchronizing the forwarded clocks between the processor and the northbridge. 5. the processor issues a connect special cycle on the system bus and resumes operating system and application code execution. stpclk # procrdy connect clkfwdrst
16 power management chapter 4 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information connect state diagram figure 6 below and figure 7 on page 17 show the northbridge and processor connect state diagrams, respectively. figure 6. northbridge connect state diagram condition 1 a disconnect is requested and probes are still pending. 2 a disconnect is requested and no probes are pending. 3 a connect special cycle from the processor. 4 no probes are pending. 5 procrdy is deasserted. 6 a probe needs service. 7 procrdy is asserted. 8 three sysclk periods after clkfwdrst is deasserted. although reconnected to the system interface, the northbridge must not issue any non-nop sysdc commands for a minimum of four sysclk periods after deasserting clkfwdrst . action a deassert connect eight sysclk periods after last sysdc sent. b assert clkfwdrst. c assert connect. d deassert clkfwdrst. disconnect pending connect disconnect requested reconnect pending probe pending 2 disconnect probe pending 1 1 3 2/a 4/a 5/b 3/c 7/d,c 8 6/c 7/d 8
chapter 4 power management 17 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information figure 7. processor connect state diagram condition 1 connect is deasserted by the northbridge (for a previously sent halt or stop grant special cycle). 2 processor receives a wake-up event and must cancel the disconnect request. 3 deassert procrdy and slow down internal clocks. 4 processor wake-up event or connect asserted by northbridge. 5 clkfwdrst is deasserted by the northbridge. 6 forward clocks start three sysclk periods after clkfwdrst is deasserted. action a clkfwdrst is asserted by the northbridge. b issue a connect special cycle.* c return internal clocks to full speed and assert procrdy. note: * the connect special cycle is only issued after a processor wake-up event (interrupt or stpclk# deassertion) occurs. if the amd athlon? system bus is connected so the northbridge can probe the processor, a connect special cycle is not issued at that time (it is only issued after a subsequent processor wake-up event). connect disconnect pending disconnect connect pending 1 connect pending 2 1 3/a 4/c 5 6/b 2/b
18 power management chapter 4 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 4.3 clock control the processor implements a clock control (clk_ctl) msr (address c001_001bh) that determines the internal clock divisor when the amd athlon system bus is disconnected. refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656, for more details on the clk_ctl register.
chapter 5 cpuid support 19 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 5 cpuid support amd athlon? xp processor model 8 version and feature set recognition can be performed through the use of the cpuid instruction, that provides complete information about the processor?vendor, type, name, etc., and its capabilities. software can make use of this information to accurately tune the system for maximum performance and benefit to users. for information on the use of the cpuid instruction see the following documents: amd processor recognition application note , order# 20734 amd athlon? processor recognition application note addendum , order# 21922 amd athlon? and amd duron? processors bios, software, and debug developers guide, order# 21656
20 cpuid support chapter 5 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 6 advanced 266 front-side bus amd athlon? xp processor model 8 specifications 21 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 6 advanced 266 front-side bus amd athlon? xp processor model 8 specifications this chapter describes the electrical specifications that are unique to the advanced 266 front-side bus (fsb) amd athlon? xp processor model 8. 6.1 part-specific electrical and thermal specifications for advanced 266 fsb amd athlon? xp processors model 8 this section provides part-specific electrical and thermal information for each type of the advanced 266 fsb amd athlon xp processors model 8 in table 1 on page 22 and table 2 on page 23.
22 advanced 266 front-side bus amd athlon? xp processor model 8 specifications chapter 6 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information table 1 shows the part-specific electrical and thermal specifications in the c0 working state and the s1 stop grant state for processors with a cpuid = 680. table 1. electrical and thermal specifications for processors with a cpuid of 680 frequency in mhz (model number) v cc_core (core voltage) i cc (processor current) thermal power 5 maximum die temperature working state c0 stop grant s1 1, 2, 3, 4 maximum typical maximum typical maximum typical 1467 (1700+) 1.50 v 32.9 a 29.9 a 5.87 a 3.7 a 49.4 w 44.9 w 90c 1533 (1800+) 34.0 a 30.9 a 51.0 w 46.3 w 1600 (1900+) 35.0 a 31.8 a 52.5 w 47.7 w 1667 (2000+) 1.60 v 37.7 a 34.2 a 7.68 a 4.7 a 60.3 w 54.7 w 1.65 v 36.5 a 33.2 a 8.85 a 5.4 a 1733 (2100+) 1.60 v 38.8 a 35.2 a 7.68 a 4.7 a 62.1 w 56.4 w 1800 (2200+) 1.65 v 41.2 a 37.4 a 8.85 a 5.4 a 67.9 w 61.7 w 85c notes: 1. see figure 3, "amd athlon? xp processor model 8 power management states" on page 9. 2. the maximum stop grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical stop grant current that is currently about one-third of the maximum specified current. 3. these currents occur when the amd athlon? system bus is disconnected and has a low power ratio of 1/8 for stop grant disconnect and a low power ratio of 1/8 halt disconnect applied to the core clock grid of the processor as dictated by a value of 6003_1223h programmed into the clock control (clk_ctl) msr. for more information, refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656. 4. the stop grant current consumption is characterized at 50c and not tested. 5. thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal v cc_core . thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature.
chapter 6 advanced 266 front-side bus amd athlon? xp processor model 8 specifications 23 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information table 2 shows the part-specific electrical and thermal specifications in the c0 working state and the s1 stop grant state for processors with a cpuid = 681. table 2. electrical and thermal specifications for processors with a cpuid of 681 frequency in mhz (model number) v cc_core (core voltage) i cc (processor current) thermal power 5 maximum die temperature working state c0 stop grant s1 1, 2, 3, 4 maximum typical maximum typical maximum typical 1533 (1800+) 1.60 v 37.4 a 34.8 a 8.1 a 4.9 a 59.8 w 55.7 w 90c 1667 (2000+) 1.60 v 38.3 a 34.8 a 8.1 a 4.9 a 61.3 w 55.7 w 1733 (2100+) 1.60 v 38.8 a 35.2 a 8.1 a 4.9 a 62.1 w 56.3 w 1800 (2200+) 1.60 v 39.3 a 35.6 a 8.1 a 4.9 a 62.8 w 57.0 w 85c 2000 (2400+) 1.65 v 41.4 a 37.6 a 8.9 a 5.4 a 68.3 w 62.0 w 2133 (2600+) 1.65 v 41.4 a 37.6 a 8.9 a 5.4 a 68.3 w 62.0 w notes: 1. see figure 3, "amd athlon? xp processor model 8 power management states" on page 9. 2. the maximum stop grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical stop grant current that is currently about one-third of the maximum specified current. 3. these currents occur when the amd athlon? system bus is disconnected and has a low power ratio of 1/8 for stop grant disconnect and a low power ratio of 1/8 halt disconnect applied to the core clock grid of the processor as dictated by a value of 2003_1223h programmed into the clock control (clk_ctl) msr. for more information, refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656. 4. the stop grant current consumption is characterized at 50c and not tested. 5. thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal v cc_core . thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature.
24 advanced 266 front-side bus amd athlon? xp processor model 8 specifications chapter 6 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 6.2 advanced 266 fsb amd athlon? xp processor model 8 sysclk and sysclk# ac characteristics table 3 shows the sysclk/sysclk# differential clock ac characteristics of this processor. . figure 8 shows a sample waveform of the sysclk signal. figure 8. sysclk waveform table 3. sysclk and sysclk# ac characteristics symbol parameter description minimum maximum units notes clock frequency 50 133 mhz 1 duty cycle 30% 70% t 1 period 7.5 ns 2, 3 t 2 high time 1.05 ns t 3 low time 1.05 ns t 4 fall time 2 ns t 5 rise time 2 ns period stability 300 ps notes: 1. the amd athlon? system bus operates at twice this clock frequency. 2. circuitry driving the amd athlon? system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow th e pll to track the jitter. the ?20db attenuation point, as measured into a 20 - or 30 - pf load must be less than 500 khz. 3. circuitry driving the amd athlon system bus clock inputs may purposely alter the amd athlon system bus clock frequency (spread spectrum clock generators). in no cases can the amd athlon system bus period violate the minimum specification above. amd athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 khz. t 5 v cross t 2 t 3 t 4 t 1 v threshold-ac
chapter 6 advanced 266 front-side bus amd athlon? xp processor model 8 specifications 25 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 6.3 advanced 266 fsb amd athlon? system bus ac characteristics the ac characteristics for the amd athlon system bus of this processor are shown in table 4. the parameters are grouped based on the source or destination of the signals involved. table 4. amd athlon? system bus ac characteristics group symbol parameter min max units notes all signals t rise output rise slew rate 1 3 v/ns 1 t fall output fall slew rate 1 3 v/ns 1 forward clocks t skew-sameedge output skew with respect to the same clock edge ?385ps2 t skew-diffedge output skew with respect to a different clock edge ?770ps2 t su input data setup time 300 ps 3 t hd input data hold time 300 ps 3 c in capacitance on input clocks 4 25 pf c out capacitance on output clocks 4 12 pf sync t val rstclk to output valid 250 2000 ps 4, 5 t su setup to rstclk 500 ps 4, 6 t hd hold from rstclk 1000 ps 4, 6 notes: 1. rise and fall time ranges are guidelines over which the i/o has been characterized. 2. t skew-sameedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. t skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. input su and hd times are with respect to the appropriate clock forward group input clock. 4. the synchronous signals include procrdy, connect, and clkfwdrst. 5. t val is rstclk rising edge to output valid for procrdy. test load is 25 pf. 6. t su is setup of connect/clkfwdrst to rising edge of rstclk. t hd is hold of connect/clkfwdrst from rising edge of rstclk.
26 advanced 266 front-side bus amd athlon? xp processor model 8 specifications chapter 6 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 7 advanced 333 front-side bus amd athlon? xp processor model 8 specifications 27 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 7 advanced 333 front-side bus amd athlon? xp processor model 8 specifications this chapter describes the electrical specifications that are unique to the advanced 333 front-side bus (fsb) amd athlon? xp processor model 8. 7.1 electrical and thermal specifications for the advanced 333 fsb amd athlon? xp processor model 8 table 5 shows the electrical and thermal specifications for this processor in the c0 working state and the s1 stop grant state. table 5. electrical and thermal specifications frequency in mhz (model number) v cc_core (core voltage) i cc (processor current) thermal power 5 maximum die temperature working state c0 stop grant s1 1, 2, 3, 4 maximum typical maximum typical maximum typical 2083 (2600+) 1.65 v 41.4 a 37.6 a 8.9 a 5.9 a 68.3 w 62.0 w 85c 2167 (2700+) notes: 1. see figure 3, "amd athlon? xp processor model 8 power management states" on page 9. 2. the maximum stop grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical stop grant current that is currently about one-third of the maximum specified current. 3. these currents occur when the amd athlon? system bus is disconnected and has a low power ratio of 1/8 for stop grant disconnect and a low power ratio of 1/8 halt disconnect applied to the core clock grid of the processor as dictated by a value of 2003_1223h programmed into the clock control (clk_ctl) msr. for more information, refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656. 4. the stop grant current consumption is characterized at 50c and not tested. 5. thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal v cc_core . thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature.
28 advanced 333 front-side bus amd athlon? xp processor model 8 specifications chapter 7 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 7.2 advanced 333 fsb amd athlon? xp processor model 8 sysclk and sysclk# ac characteristics table 6 shows the sysclk/sysclk# differential clock ac characteristics of this processor. figure 9 shows a sample waveform of the sysclk signal. figure 9. sysclk waveform table 6. sysclk and sysclk# ac characteristics symbol parameter description minimum maximum units notes clock frequency 50 166 mhz 1 duty cycle 30% 70% t 1 period 6 ns 2, 3 t 2 high time 1.05 ns t 3 low time 1.05 ns t 4 fall time 2 ns t 5 rise time 2 ns period stability 300 ps notes: 1. the amd athlon system bus operates at twice this clock frequency. 2. circuitry driving the amd athlon? system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow th e pll to track the jitter. the ?20db attenuation point, as measured into a 20 - or 30 - pf load must be less than 500 khz. 3. circuitry driving the amd athlon system bus clock inputs may purposely alter the amd athlon system bus clock frequency (spread spectrum clock generators). in no cases can the amd athlon system bus period violate the minimum specification above. amd athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 khz. t 5 v cross t 2 t 3 t 4 t 1 v threshold-ac
chapter 7 advanced 333 front-side bus amd athlon? xp processor model 8 specifications 29 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 7.3 advanced 333 fsb amd athlon? system bus ac characteristics the ac characteristics of the amd athlon system bus of this processor are shown in table 7. the parameters are grouped based on the source or destination of the signals involved. table 7. amd athlon? system bus ac characteristics group symbol parameter min max units notes all signals t rise output rise slew rate 1 3 v/ns 1 t fall output fall slew rate 1 3 v/ns 1 forward clocks t skew-diffedge output skew with respect to a different clock edge ?770ps2 t su input data setup time 300 ps 3 t hd input data hold time 300 ps 3 c in capacitance on input clocks 4 25 pf c out capacitance on output clocks 4 12 pf sync t val rstclk to output valid 800 2000 ps 4, 5 t su setup to rstclk 500 ps 4, 6 t hd hold from rstclk 500 ps 4, 6 notes: 1. rise and fall time ranges are guidelines over which the i/o has been characterized. 2. t skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. input su and hd times are with respect to the appropriate clock forward group input clock. 4. the synchronous signals include procrdy, connect, and clkfwdrst. 5. t val is rstclk rising edge to output valid for procrdy. test load is 25 pf. 6. t su is setup of connect/clkfwdrst to rising edge of rstclk. t hd is hold of connect/clkfwdrst from rising edge of rstclk.
30 advanced 333 front-side bus amd athlon? xp processor model 8 specifications chapter 7 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 8 electrical data 31 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 8 electrical data this chapter describes the electr ical characteristics that apply to all desktop amd athlon? xp processors model 8. 8.1 conventions the conventions used in this chapter are as follows: current specified as being sourced by the processor is negative . current specified as being sunk by the processor is positive . 8.2 interface signal groupings the electrical data in this chapter is presented separately for each signal group. table 8 defines each group and the signals contained in each group. table 8. interface signal groupings signal group signals notes amd athlon? system bus saddin[14:2]#, saddout[14:2]#, saddinclk#, saddoutclk#, sfillval#, sdatainval#, sdataoutval#, sdata[63:0]#, sdatainclk[3:0]#, sdataoutclk[3:0]#, clkfwdrst, procrdy, connect see ?advanced 266 fsb amd athlon? system bus ac characteristics? on page 25, ?advanced 333 fsb amd athlon? system bus ac characteristics? on page 29, ?amd athlon? system bus dc characteristics? on page 36, and ?clkfwdrst pin? on page 71. apic picd[1:0]#, picclk see ?apic pins ac and dc characteristics? on page 44, and ?apic pins, picclk, picd[1:0]#? on page 71. frequency fid[3:0], fsb_sense[1:0] see ?frequency identification (fid[3:0])? on page 33, ?fid[3:0] pins? on page 73, and ?fsb_sense[1:0] pins? on page 74. jtag tms, tck, trst#, tdi, tdo see ?general ac and dc characteristics? on page 39.
32 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information power vid[4:0], vcca, v cc_core , corefb, corefb# see ?voltage identification (vid[4:0])? on page 33, ?vid[4:0] pins? on page 76,?vcca ac and dc characteristics? on page 33, ?v cc_core characteristics? on page 34,?vcca pin? on page 76, and ?corefb and corefb# pins? on page 72. southbridge reset#, intr, nmi, smi#, init#, a20m#, ferr, ignne#, stpclk#, flush# see ?general ac and dc characteristics? on page 39, ?intr pin? on page 74, ?nmi pin? on page 75, ?smi# pin? on page 76, ?init# pin? on page 74, ?a20m# pin? on page 71, ?ferr pin? on page 72,?ignne# pin? on page 74, ?stpclk# pin? on page 76, and ?flush# pin? on page 74. system clocks sysclk, sysclk# (tied to clkin/clkin# and rstclk/rstclk#), pllbypassclk#, pllbypassclk see ?advanced 266 fsb amd athlon? xp processor model 8 sysclk and sysclk# ac characteristics? on page 24, ?advanced 333 fsb amd athlon? xp processor model 8 sysclk and sysclk# ac characteristics? on page 28, table 14, ?sysclk and sysclk# dc characteristics,? on page 37, ?sysclk and sysclk#? on page 76, and ?pll bypass and test pins? on page 75. test pllbypass#, plltest#, pllmon1, pllmon2, scanclk1, scanclk2, scanshiften, scaninteval, analog see ?general ac and dc characteristics? on page 39, ?pll bypass and test pins? on page 75, ?scan pins? on page 76, ?analog pin? on page 71. thermal thermda, thermdc table 17, ?thermal diode electrical characteristics,? on page 42, and ?thermda and thermdc pins? on page 76. miscellaneous dbreq#, dbrdy, pwrok see ?general ac and dc characteristics? on page 39, ?dbrdy and dbreq# pins? on page 72, ?pwrok pin? on page 75. table 8. interface signal groupings (continued) signal group signals notes
chapter 8 electrical data 33 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 8.3 voltage identification (vid[4:0]) table 9 shows the vid[4:0] dc characteristics. for more infor- mation on vid[4:0] dc characteristics, see ?vid[4:0] pins? on page 76. 8.4 frequency identification (fid[3:0]) table 10 shows the fid[3:0] dc characteristics. for more information, see ?fid[3:0] pins? on page 73. 8.5 vcca ac and dc characteristics table 11 shows the ac and dc characteristics for vcca. for more information, see ?vcca pin? on page 76. table 9. vid[4:0] dc characteristics parameter description min max i ol output current low 6 ma v oh output high voltage ? 5.25 v * note: * the vid pins are either open circuit or pulled to ground. it is recommended that these pins are not pulled above 5.25 v, which is 5.0 v + 5%. table 10. fid[3:0] dc characteristics parameter description min max i ol output current low 6 ma v oh output high voltage ? 2.625 v * note: * the fid pins must not be pulled above this voltage by an external pullup resistor. table 11. vcca ac and dc characteristics symbol parameter min nominal max units notes v vcca vcca pin voltage 2.25 2.5 2.75 v 1 i vcca vcca pin current 0 50 ma/ghz 2 notes: 1. minimum and maximum voltages are absolute. no transients below minimum nor above maximum voltages are permitted. 2. measured at 2.5 v.
34 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.6 decoupling see the amd athlon? processor-based motherboard design guide , order# 24363, or contact your local amd office for information about the decoupling required on the motherboard for use with the amd athlon? xp processor model 8. 8.7 v cc_core characteristics table 12 shows the ac and dc characteristics for v cc_core . see figure 10 on page 35 for a graphical representation of the v cc_core waveform. table 12. v cc_core ac and dc characteristics symbol parameter limit in working state units v cc_core_dc_max maximum static voltage above v cc_core_nom * 50 mv v cc_core_dc_min maximum static voltage below v cc_core_nom * ?50 mv v cc_core_ac_max maximum excursion above v cc_core_nom * 150 mv v cc_core_ac_min maximum excursion below v cc_core_nom * ?100 mv t max_ac maximum excursion time for ac transients 10 s t min_ac negative excursion time for ac transients 5 s note: * all voltage measurements are taken differentially at the corefb/corefb# pins.
chapter 8 electrical data 35 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information figure 10 shows the processor core voltage (v cc_core ) waveform response to perturbation. the t min_ac (negative ac transient excursion time) and t max_ac (positive ac transient excursion time) represent the maximum allowable time below or above the dc tolerance thresholds. figure 10. v cc_core voltage waveform t min_ac v cc_core_ac_max t max_ac v cc_core_dc_max v cc_core_nom v cc_core_dc_min v cc_core_ac_min i core_min i core_max di /dt
36 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.8 absolute ratings the amd athlon xp processor model 8 should not be subjected to conditions exceeding the absolute ratings, as such conditions can adversely affect long-term reliability or result in functional damage. table 13 lists the maximum absolute ratings of operation for the amd athlon xp processor model 8. table 13. absolute ratings parameter description min max v cc_core amd athlon? xp processor model 8 core supply ?0.5 v v cc_core max + 0.5 v vcca amd athlon xp processor model 8 pll supply ?0.5 v vcca max + 0.5 v v pin voltage on any signal pin ?0.5 v v cc_core max + 0.5 v t storage storage temperature of processor ?40oc 100oc
chapter 8 electrical data 37 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 8.9 sysclk and sysclk# dc characteristics table 14 shows the dc characteristics of the sysclk and sysclk# differential clocks. the sysclk signal represents clkin and rstclk tied together while the sysclk# signal represents clkin# and rstclk# tied together. for information about sysclk and sysclk#, see ?sysclk and sysclk#? on page 76 and table 23, ?pin name abbreviations,? on page 56. figure 11 shows the dc characteristics of the sysclk and sysclk# signals. figure 11. sysclk and sysclk# differential clock signals table 14. sysclk and sysclk# dc characteristics symbol description min max units v threshold-dc crossing before transition is detected (dc) 400 mv v threshold-ac crossing before transition is detected (ac) 450 mv i leak_p leakage current through p-channel pullup to v cc_core ?1 ma i leak_n leakage current through n-channel pulldown to vss (ground) 1 ma v cross differential signal crossover v cc_core / 2100 mv c pin capacitance * 4 25 * pf note: * the following processor inputs have twice the listed capacitance because they connect to two input pads?sysclk and sysclk#. sysclk connects to clkin/rstclk. sysclk# connects to clkin#/rstclk#. v cross v threshold-dc = 400mv v threshold-ac = 450mv
38 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.10 amd athlon? system bus dc characteristics table 15 shows the dc characteristics of the amd athlon system bus used by the amd athlon xp processor model 8. table 15. amd athlon? system bus dc characteristics symbol parameter condition min max units notes v ref dc input reference voltage (0.5 x v cc_core ) ?50 (0.5 x v cc_core ) +50 mv 1 i vref_leak_p v ref tristate leakage pullup v in = v ref nominal ?100 a i vref_leak_n v ref tristate leakage pulldown v in = v ref nominal 100 a v ih input high voltage v ref + 200 v cc_core + 500 mv v il input low voltage ?500 v ref ? 200 mv i leak_p tristate leakage pullup v in = vss (ground) ?1 ma i leak_n tristate leakage pulldown v in = v cc_core nominal 1ma c in input pin capacitance 4 7 pf r on output resistance 0.90 x r setn,p 1.1 x r setn,p ? 2 r setp impedance set point, p channel 40 70 ? 2 r setn impedance set point, n channel 40 70 ? 2 notes: 1. v ref is nominally set to 50% of v cc_core with actual values that are specific to motherboard design implementation. v ref must be created with a sufficiently accurate dc source and a sufficiently quiet ac response to adhere to the 50 mv specification list ed above. 2. measured at v cc_core / 2.
chapter 8 electrical data 39 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 8.11 general ac and dc characteristics table 16 shows the amd athlon xp processor model 8 ac and dc characteristics of the southbridge, jtag, test, and miscel- laneous pins. table 16. general ac and dc characteristics symbol parameter description condition min max units notes v ih input high voltage (v cc_core / 2) + 200 mv v cc_core + 300 mv v1,2 v il input low voltage ?300 350 mv 1, 2 v oh output high voltage v cc_core ? 400 v cc_core + 300 mv v ol output low voltage ?300 400 mv i leak_p tristate leakage pullup v in = vss (ground) ?1 ma i leak_n tristate leakage pulldown v in = v cc_core nominal 600 a i oh output high current ?16 ma 3 i ol output low current 16 ma 3 t su sync input setup time 2.0 ns 4, 5 t hd sync input hold time 0.0 ps 4, 5 t delay output delay with respect to rstclk 0.0 6.1 ns 5 notes: 1. characterized across dc supply voltage range. 2. values specified at nominal v cc_core . scale parameters between v cc_core. minimum and v cc_core. maximum. 3. i ol and i oh are measured at v ol maximum and v oh minimum, respectively. 4. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 5. these are aggregate numbers. 6. edge rates indicate the range over which inputs were characterized. 7. in asynchronous operation, the signal must persist for this time to enable capture. 8. this value assumes rstclk period is 10 ns ==> tbit = 2*frst. 9. the approximate value for standard case in normal mode operation. 10. this value is dependent on rstclk frequency, divisors, low power mode, and core frequency. 11. reassertions of the signal within this time are not guaranteed to be seen by the core. 12. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 13. this value assumes rstclk and k7clkout are running at the same frequency, though the processor is capable of other configurations. 14. time to valid is for any open-drain pins. see requirements 7 and 8 in the ?power-up timing requirements? chapter for more information.
40 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information t bit input time to acquire 20.0 ns 7, 8 t rpt input time to reacquire 40.0 ns 9?13 t rise signal rise time 1.0 3.0 v/ns 6 t fall signal fall time 1.0 3.0 v/ns 6 c p in pin capacitance 4 12 pf t valid time to data valid 100 ns 14 table 16. general ac and dc characteristics (continued) symbol parameter description condition min max units notes notes: 1. characterized across dc supply voltage range. 2. values specified at nominal v cc_core . scale parameters between v cc_core. minimum and v cc_core. maximum. 3. i ol and i oh are measured at v ol maximum and v oh minimum, respectively. 4. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 5. these are aggregate numbers. 6. edge rates indicate the range over which inputs were characterized. 7. in asynchronous operation, the signal must persist for this time to enable capture. 8. this value assumes rstclk period is 10 ns ==> tbit = 2*frst. 9. the approximate value for standard case in normal mode operation. 10. this value is dependent on rstclk frequency, divisors, low power mode, and core frequency. 11. reassertions of the signal within this time are not guaranteed to be seen by the core. 12. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 13. this value assumes rstclk and k7clkout are running at the same frequency, though the processor is capable of other configurations. 14. time to valid is for any open-drain pins. see requirements 7 and 8 in the ?power-up timing requirements? chapter for more information.
chapter 8 electrical data 41 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 8.12 open-drain test circuit figure 12 is a test circuit that may be used on automated test equipment (ate) to test for validity on open drain pins. refer to table 16, ?general ac and dc characteristics,? on page 39 for timing requirements. figure 12. general ate open-drain test circuit open-drain pin v termination 1 50 ? 3% i ol = output current 2 notes: 1. v termination = 1.2 v for vid and fid pins v termination = 1.0 v for apic pins 2. i ol = ?16 ma for vid and fid pins i ol = ?12 ma for apic pins
42 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.13 thermal diode characteristics the amd athlon xp processor model 8 provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor. the diode anode (thermda) and cathode (thermdc) are available as pins on the processor, as described in ?thermda and thermdc pins? on page 76. for information about thermal design for the amd athlon xp processor model 8, including layout and airflow considerations, see the amd processor thermal, mechanical, and chassis cooling design guide , order# 23794, and the cooling guidelines on http://www.amd.com . thermal diode electrical characteristics table 17 shows the amd athlon xp processor model 8 characteristics of the on-die thermal diode. for information about calculations for the ideal diode equation and temperature offset correction, see appendix a, "thermal diode calculations," on page 77. table 17. thermal diode electrical characteristics symbol parameter description min nom max units notes i sourcing current 5 300 a 1 n f, lumped lumped ideality factor 1.00000 1.00374 1.00900 2, 3, 4 n f, actual actual ideality factor 1.00261 3, 4 r t series resistance 0.93 ? 3, 4 notes: 1. the sourcing current should always be used in forward bias only. 2. characterized at 95c with a forward bias current pair of 10 a and 100 a. amd recommends using a minimum of two sourcing currents to accurately measure the temperature of the thermal diode. 3. not 100% tested. specified by design and limited characterization. 4. the lumped ideality factor adds the effect of the series resistance term to the actual ideality factor. the series resistance term indicates the resistance from the pins of the processor to the on-die thermal diode. the value of the lumped ideality factor depends on the sourcing current pair used.
chapter 8 electrical data 43 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information thermal protection characterization the following section describes pa rameters relating to thermal protection. the implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement. thermal limits in motherboard design are necessary to protect the processor from thermal damage. t shutdown is the temperature for thermal protection circuitry to initiate shutdown of the processor. t sd_delay is the maximum time allowed from the detection of the over-temperature condition to processor shutdown to prevent thermal damage to the processor. systems that do not implement thermal protection circuitry or that do not react within the time specified by t sd_delay can cause thermal damage to the processor during the unlikely events of fan failure or powering up the processor without a heat-sink. the processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents: amd athlon? processor-based motherboard design guide, order# 24363 amd thermal, mechanical, and chassis cooling design guide , order# 23794 see http://www.amd.com for more information about thermal solutions. table 18 on page 44 shows the t shutdown and t sd_delay specifications for circuitry in motherboard design necessary for thermal protection of the processor.
44 electrical data chapter 8 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 8.14 apic pins ac and dc characteristics table 19 shows the amd athlon xp processor model 8 ac and dc characteristics of the apic pins. table 18. guidelines for platform thermal protection of the processor symbol parameter description max units notes t shutdown thermal diode shutdown temperature for processor protection 125 c1, 2, 3 t sd_delay maximum allowed time from t shutdown detection to processor shutdown 500 ms 1, 3 notes: 1. the thermal diode is not 100% tested, it is specified by design and limited characterization. 2. the thermal diode is capable of responding to thermal events of 40c/s or faster. 3. the amd athlon? xp processor model 8 provides a thermal diode for measuring die temperature of the processor. the processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. refer to amd athlon? processor-based motherboard design guide , order# 24363, for thermal protection circuitry designs. table 19. apic pin ac and dc characteristics symbol parameter description condition min max units notes v ih input high voltage 1.7 2.625 v 1, 2 v il input low voltage ?300 700 mv 1 v oh output high voltage 2.625 v 2 v ol output low voltage ?300 400 mv i leak_p tristate leakage pullup v in = vss (ground) ?1 ma i leak_n tristate leakage pulldown v in = 2.5 v 1ma i ol output low current v ol max 9ma t rise signal rise time 1.0 3.0 v/ns 3 t fall signal fall time 1.0 3.0 v/ns 3 t su setup time 1 ns t hd hold time 1 ns c pin pin capacitance 4 12 pf notes: 1. characterized across dc supply voltage range. 2. the 2.625-v value is equal to 2.5 v plus a maximum of five percent. 3. edge rates indicate the range for characterizing the inputs.
chapter 9 signal and power-up requirements 45 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 9 signal and power-up requirements the amd athlon? xp processor model 8 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges. 9.1 power-up requirements signal sequence and timing description figure 13 shows the relationship between key signals in the system during a power-up sequence. this figure details the requirements of the processor. figure 13. signal relationship requirements during power-up sequence notes: 1. figure 13 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. 2. requirements 1?8 in figure 13 are described in ?power-up timing requirements? on page 46. 3.3 v supply vcca (2.5 v) (for pll) reset# v cc_core nb_reset# pwrok system clock 2 1 3 4 5 6 fid[3:0] 7 8 warm reset condition
46 signal and power-up requirements chapter 9 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information power-up timing requirements. the signal timing requirements are as follows: 1. reset# must be asserted before pwrok is asserted. the amd athlon xp processor model 8 does not set the correct clock multiplier if pwrok is asserted prior to a reset# assertion. it is recommended that reset# be asserted at least 10 nanoseconds prior to the assertion of pwrok. in practice, a southbridge asserts reset# milliseconds before pwrok is asserted. 2. all motherboard voltage planes must be within specification before pwrok is asserted. pwrok is an output of the voltage regulation circuit on the motherboard. pwrok indicates that v cc_core and all other voltage planes in the system are within specification. the motherboard is required to delay pwrok assertion for a minimum of three milliseconds from the 3.3 v supply being within specification. this delay ensures that the system clock (sysclk/sysclk#) is operating within specification when pwrok is asserted. the processor core voltage, v cc_core , must be within specification as dictated by the vid[4:0] pins driven by the processor before pwrok is asserted. before pwrok assertion, the amd athlon processor is clocked by a ring oscillator. the processor pll is powered by vcca. the processor pll does not lock if vcca is not high enough for the processor logic to switch for some period before pwrok is asserted. vcca must be within specification at least five microseconds before pwrok is asserted. in practice vcca, v cc_core , and all other voltage planes must be within specification for several milliseconds before pwrok is asserted. after pwrok is asserted, the processor pll locks to its operational frequency. 3. the system clock (sysclk/sysclk#) must be running before pwrok is asserted. when pwrok is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the pll. the reference system
chapter 9 signal and power-up requirements 47 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information clock must be valid at this time. the system clocks are designed to be running after 3.3 v has been within specification for three milliseconds. 4. pwrok assertion to deassertion of reset# the duration of reset# assertion during cold boots is intended to satisfy the time it takes for the pll to lock with a less than 1 ns phase error. the processor pll begins to run after pwrok is asserted and the internal clock grid is switched from the ring oscillator to the pll. the pll lock time may take from hundreds of nanoseconds to tens of microseconds. it is recommended that the minimum time between pwrok assertion to the deassertion of reset# be at least 1.0 milliseconds . southbridges enforce a delay of 1.5 to 2.0 milliseconds between pwrgd (southbridge version of pwrok) assertion and nb_reset# deassertion. 5. pwrok must be monotonic and meet the timing requirements as defined in table 16, ?general ac and dc characteristics,? on page 39. the processor should not switch between the ring oscillator and the pll after the initial assertion of pwrok. 6. nb_reset# must be asserted (causing connect to also assert) before reset# is deasserted. in practice all southbridges enforce this requirement. if nb_reset# does not assert until after reset# has deasserted, the processor misinterprets the connect assertion (due to nb_reset# being asserted) as the beginning of the sip transfer. there must be sufficient overlap in the resets to ensure that connect is sampled asserted by the processor before reset# is deasserted. 7. the fid[3:0] signals are valid within 100 ns after pwrok is asserted. the chipset must not sample the fid[3:0] signals until they become valid. refer to the amd athlon? processor-based motherboard design guide , order# 24363, for the specific implementation and additional circuitry required. 8. the fid[3:0] signals become valid within 100 ns after reset# is asserted. refer to the amd athlon? processor- based motherboard design guide , order# 24363, for the specific implementation and additional circuitry required.
48 signal and power-up requirements chapter 9 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information clock multiplier selection (fid[3:0]) the chipset samples the fid[3:0] signals in a chipset-specific manner from the processor and uses this information to determine the correct serial initialization packet (sip). the chipset then sends the sip information to the processor for configuration of the amd athlon system bus for the clock multiplier that determines the processor frequency indicated by the fid[3:0] code. the sip is sent to the processor using the sip protocol. this protocol uses the procrdy, connect, and clkfwdrst signals, that are synchronous to sysclk. for more information about fid[3:0], see ?fid[3:0] pins? on page 73. serial initialization packet (sip) protocol. refer to amd athlon? system bus specification , order# 21902 for details of the sip protocol. 9.2 processor warm reset requirements northbridge reset pins reset# cannot be asserted to the processor without also being asserted to the northbridge. reset# to the northbridge is the same as pci reset#. the minimum assertion for pci reset# is one millisecond. southbridges enforce a minimum assertion of reset# for the processor, northbridge, and pci of 1.5 to 2.0 milliseconds.
chapter 10 mechanical data 49 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 10 mechanical data 10.1 introduction the amd athlon? xp processor model 8 connects to the motherboard through a pin grid array (pga) socket named socket a. this processor utilizes the organic pin grid array (opga) package type described in this section. for more information, see the amd athlon? processor-based motherboard design guide , order# 24363. 10.2 die loading the processor die on the opga package is exposed at the top of the package. this feature facilitat es heat transfer from the die to an approved heat sink. any heat sink design should avoid loads on corners and edges of die. the opga package has compliant pads that serve to bring surfaces in planar contact. tool-assisted zero insertion force sockets should be designed so that no load is placed on the substrate of the package. table 20 shows the mechanical loading specifications for the processor die. it is critical that the mechanical loading of the heat sink does not exceed the limits shown in table 20. table 20. mechanical loading location dynamic (max) static (max) units note die surface 100 30 lbf 1 die edge 10 10 lbf 2 notes: 1. load specified for coplanar contact to die surface. 2. load defined for a surface at no more than a two-degree angle of inclination to die surface.
50 mechanical data chapter 10 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 10.3 opga package dimensions of amd athlon? xp processors model 8 with a cpuid of 680 figure 14 on page 52 shows a diagram and notes for the opga package of this processor. table 21 provides the dimensions in millimeters assigned to the letters and symbols shown in the figure 14 diagram. table 21. opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 680 letter or symbol minimum dimension 1 maximum dimension 1 letter or symbol minimum dimension 1 maximum dimension 1 d/e 49.27 49.78 e9 1.66 1.96 d1/e1 45.72 bsc g/h ? 4.50 d2 7.31 ref a 1.942 ref d3 3.30 3.60 a1 1.00 1.20 d4 10.78 11.33 a2 0.80 0.88 d5 10.78 11.33 a3 0.116 ? d6 8.13 8.68 a4 ? 1.90 d7 12.33 12.88 p ? 6.60 d8 3.05 3.35 b 0.43 0.50 d9 12.71 13.26 b1 1.40 ref e2 11.06 ref s 1.435 2.375 e3 2.35 2.65 l 3.05 3.31 e4 7.87 8.42 m 37 e5 7.87 8.42 n 453 e6 10.73 11.28 e 1.27 bsc e7 10.73 11.28 e1 2.54 bsc e8 13.28 13.83 mass 2 11.0 g ref note: 1. dimensions are given in millimeters. 2. the mass consists of the completed package, including processor, surface mounted parts and pins.
chapter 10 mechanical data 51 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 10.4 opga package dimensions of amd athlon? xp processors model 8 with a cpuid of 681 figure 14 on page 52 shows the mechanical diagram and notes for the opga package of this processor. table 22 provides the dimensions in millimeters assigned to the letters and symbols shown in the figure 14 diagram. table 22. opga package dimensions for amd athlon? xp processors model 8 with a cpuid of 681 letter or symbol minimum dimension 1 maximum dimension 1 letter or symbol minimum dimension 1 maximum dimension 1 d/e 49.27 49.78 e9 1.66 1.96 d1/e1 45.72 bsc g/h ? 4.50 d2 7.47 ref a 1.942 ref d3 3.30 3.60 a1 1.00 1.20 d4 10.78 11.33 a2 0.80 0.88 d5 10.78 11.33 a3 0.116 ? d6 8.13 8.68 a4 ? 1.90 d7 12.33 12.88 p ? 6.60 d8 3.05 3.35 b 0.43 0.50 d9 12.71 13.26 b1 1.40 ref e2 11.33 ref s 1.435 2.375 e3 2.35 2.65 l 3.05 3.31 e4 7.87 8.42 m 37 e5 7.87 8.42 n 453 e6 10.73 11.28 e 1.27 bsc e7 10.73 11.28 e1 2.54 bsc e8 13.28 13.83 mass 2 11.0 g ref note: 1. dimensions are given in millimeters. 2. the mass consists of the completed package, including processor, surface mounted parts and pins.
52 mechanical data chapter 10 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information figure 14. amd athlon? xp processor model 8 opga package
chapter 11 pin descriptions 53 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 11 pin descriptions 11.1 pin diagram and pin name abbreviations figure 15 on page 54 shows the st aggered pin grid array (pga) for the amd athlon? xp processor model 8. because some of the pin names are too long to fit in the grid, they are abbreviated. figure 16 on page 55 shows the bottomside view of the array. table 23 on page 56 lists all the pins in alphabetical order by pin name, along with the abbreviation where necessary.
54 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information 12345678910111213141516171819202122232425262728 293031323334353637 a sao#12 sao#5 sao#3 sd#55 sd#61 sd#53 sd#63 sd#62 nc sd#57 sd#39 sd#35 sd#34 sd#44 nc sdoc#2 sd#40 sd#30 a b vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc b c sao#7 sao#9 sao#8 sao#2 sd#54 sdoc#3 nc sd#51 sd#60 sd#59 sd#56 sd#37 sd#47 sd#38 sd#45 sd#43 sd#42 sd#41 sdoc#1 c d vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss d e sao#11 saoc# sao#4 sao#6 sd#52 sd#50 sd#49 sdic#3 sd#48 sd#58 sd#36 sd#46 nc sdic#2 sd#33 sd#32 nc sd#31 sd#22 e f vss vss vss nc vss vcc vss vcc vss vcc vss vcc vss vcc nc vcc vcc vcc f g sao#10 sao#14 sao#13 key key nc nc key key nc nc key key nc nc nc sd#20 sd#23 sd#21 g h vcc vcc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc vss vss h j sao#0 sao#1 nc vid[4] nc sd#19 sdic#1 sd#29 j k vss vss vss nc nc vcc vcc vcc k l vid[0] vid[1] vid[2] vid[3] nc sd#26 nc sd#28 l m vcc vcc vcc vcc vss vss vss vss m n picclk picd#0 picd#1 key nc sd#25 sd#27 sd#18 n p vss vss vss vss vcc vcc vcc vcc p q tck tms scnsn key nc sd#24 sd#17 sd#16 q r vcc vcc vcc vcc vss vss vss vss r s scnck1 scninv scnck2 thda nc sd#7 sd#15 sd#6 s t vss vss vss vss vcc vcc vcc vcc t u tdi trst# tdo thdc nc sd#5 sd#4 nc u v vcc vcc vcc vcc vss vss vss vss v w fid[0] fid[1] vref_s nc nc sdic#0 sd#2 sd#1 w x vss vss vss vss vcc vcc vcc vcc x y fid[2] fid[3] nc key nc nc sd#3 sd#12 y z vcc vcc vcc vcc vss vss vss vss z aa dbrdy dbreq# nc key nc sd#8 sd#0 sd#13 aa ab vss vss vss vss vcc vcc vcc vcc ab ac stpc# pltst# zn nc nc sd#10 sd#14 sd#11 ac ad vcc vcc vcc nc nc vss vss vss ad ae a20m# pwrok zp nc nc sai#5 sdoc#0 sd#9 ae af vss vss nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc vcc vcc af ag ferr reset# nc key key corefb corefb# key key nc nc nc nc key key fsb0 sai#2 sai#11 sai#7 ag ah vcc vcc amd nc vcc vss vcc vss vcc vss vcc vss vcc vss fsb1 vss vss vss ah aj ignne# init# vcc nc nc nc anlog nc nc nc clkfr vcca plbyp# nc sai#0 sfillv# saic# sai#6 sai#3 aj ak vss vss cpr# nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc ak al intr flush# vcc nc nc nc plmn2 plbyc# clkin# rclk# k7co cnnct nc nc sai#1 sdov# sai#8 sai#4 sai#10 al am vcc vss vss nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss am an nmi smi# nc nc nc plmn1 plbyc clkin rclk k7co# prcrdy nc nc sai#12 sai#14 sdinv# sai#13 sai#9 an 12345678910111213141516171819202122232425262728 293031323334353637 amd athlon? xp processor model 8 topside view figure 15. amd athlon? xp processor model 8 pin diagram?topside view
chapter 11 pin descriptions 55 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information a b c d e f g h j k l m n p q r s t u v w x y z aa ab ac ad ae af ag ah aj ak al am an 1 sao#7 sao#11 sao#10 sao#0 vid[0] picclk tck scnck1 tdi fid[0] fid[2] dbrdy stpc# a20m# ferr ignne# intr 1 2 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc 2 3 sao#12 sao#9 saoc# sao#14 sao#1 vid[1] picd#0 tms scninv trst# fid[1] fid[3] dbreq# pltst# pwrok reset# init# flush# nmi 3 4 vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss 4 5 sao#5 sao#8 sao#4 sao#13 nc vid[2] picd#1 scnsn scnck2 tdo vref_s nc nc zn zp nc vcc vcc smi# 5 6 vss vss vss nc vss vcc vss vcc vss vcc vss vcc vss vcc nc amd cpr# vss 6 7 sao#3 sao#2 sao#6 key vid[4] vid[3] key key thda thdc nc key key nc nc key nc nc nc 7 8 vcc vcc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc 8 9 sd#55 sd#54 sd#52 key key nc nc nc 9 10 vss vss vss nc nc vcc vcc vcc 10 11 sd#61 sdoc#3 sd#50 nc corefb nc nc nc 11 12 vcc vcc vcc vcc vss vss vss vss 12 13 sd#53 nc sd#49 nc corefb# anlog plmn2 plmn1 13 14 vss vss vss vss vcc vcc vcc vcc 14 15 sd#63 sd#51 sdic#3 key key nc plbyc# plbyc 15 16 vcc vcc vcc vcc vss vss vss vss 16 17 sd#62 sd#60 sd#48 key key nc clkin# clkin 17 18 vss vss vss vss vcc vcc vcc vcc 18 19 nc sd#59 sd#58 nc nc nc rclk# rclk 19 20 vcc vcc vcc vcc vss vss vss vss 20 21 sd#57 sd#56 sd#36 nc nc clkfr k7co k7co# 21 22 vss vss vss vss vcc vcc vcc vcc 22 23 sd#39 sd#37 sd#46 key nc vcca cnnct prcrdy 23 24 vcc vcc vcc vcc vss vss vss vss 24 25 sd#35 sd#47 nc key nc plbyp# nc nc 25 26 vss vss vss vss vcc vcc vcc vcc 26 27 sd#34 sd#38 sdic#2 nc key nc nc nc 27 28 vcc vcc vcc nc nc vss vss vss 28 29 sd#44 sd#45 sd#33 nc key sai#0 sai#1 sai#12 29 30 vss vss nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc fsb1 vcc vcc 30 31 nc sd#43 sd#32 nc nc nc nc nc nc nc nc nc nc nc nc fsb0 sfillv# sdov# sai#14 31 32 vcc vcc vcc nc vcc vss vcc vss vcc vss vcc vss vcc vss nc vss vss vss 32 33 sdoc#2 sd#42 nc sd#20 sd#19 sd#26 sd#25 sd#24 sd#7 sd#5 sdic#0 nc sd#8 sd#10 sai#5 sai#2 saic# sai#8 sdinv# 33 34 vss vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc 34 35 sd#40 sd#41 sd#31 sd#23 sdic#1 nc sd#27 sd#17 sd#15 sd#4 sd#2 sd#3 sd#0 sd#14 sdoc#0 sai#11 sai#6 sai#4 sai#13 35 36 vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss 36 37 sd#30 sdoc#1 sd#22 sd#21 sd#29 sd#28 sd#18 sd#16 sd#6 nc sd#1 sd#12 sd#13 sd#11 sd#9 sai#7 sai#3 sai#10 sai#9 37 a b c d e f g h j k l m n p q r s t u v w x y z aa ab ac ad ae af ag ah aj ak al am an amd athlon? xp processor model 8 bottomside view figure 16. amd athlon? xp processor model 8 pin diagram?bottomside view
56 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information table 23. pin name abbreviations abbreviation full name pin a20m# ae1 amd ah6 anlog analog aj13 clkfr clkfwdrst aj21 clkin an17 clkin# al17 cnnct connect al23 corefb ag11 corefb# ag13 cpr# cpu_presence# ak6 dbrdy aa1 dbreq# aa3 ferr ag1 fid[0] w1 fid[1] w3 fid[2] y1 fid[3] y3 flush# al3 fsb0 fsb_sense[0] ag31 fsb1 fsb_sense[1] ah30 ignne# aj1 init# aj3 intr al1 k7co k7clkout al21 k7co# k7clkout# an21 key g7 key g9 key g15 key g17 key g23 key g25 key n7 key q7 key y7 key aa7 key ag7 key ag9 key ag15 key ag17 key ag27 key ag29 nc a19 nc a31 nc c13 nc e25 nc e33 nc f8 nc f30 nc g11 nc g13 nc g19 nc g21 nc g27 nc g29 nc g31 nc h6 nc h8 nc h10 nc h28 nc h30 nc h32 nc j5 nc j31 nc k8 nc k30 nc l31 nc l35 nc n31 nc q31 nc s31 nc u31 nc u37 nc w7 nc w31 nc y5 nc y31 nc y33 nc aa5 table 23. pin name abbreviations (continued) abbreviation full name pin
chapter 11 pin descriptions 57 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information nc aa31 nc ac7 nc ac31 nc ad8 nc ad30 nc ae7 nc ae31 nc af6 nc af8 nc af10 nc af28 nc af30 nc af32 nc ag5 nc ag19 nc ag21 nc ag23 nc ag25 nc ah8 nc aj7 nc aj9 nc aj11 nc aj15 nc aj17 nc aj19 nc aj27 nc ak8 nc al7 nc al9 nc al11 nc al25 nc al27 nc am8 nc an7 nc an9 nc an11 nc an25 nc an27 nmi an3 table 23. pin name abbreviations (continued) abbreviation full name pin picclk n1 picd#0 picd[0]# n3 picd#1 picd[1]# n5 plbyp# pllbypass# aj25 plbyc pllbypassclk an15 plbyc# pllbypassclk# al15 plmn1 pllmon1 an13 plmn2 pllmon2 al13 pltst# plltest# ac3 prcrdy procready an23 pwrok ae3 reset# ag3 rclk rstclk an19 rclk# rstclk# al19 sai#0 saddin[0]# aj29 sai#1 saddin[1]# al29 sai#2 saddin[2]# ag33 sai#3 saddin[3]# aj37 sai#4 saddin[4]# al35 sai#5 saddin[5]# ae33 sai#6 saddin[6]# aj35 sai#7 saddin[7]# ag37 sai#8 saddin[8]# al33 sai#9 saddin[9]# an37 sai#10 saddin[10]# al37 sai#11 saddin[11]# ag35 sai#12 saddin[12]# an29 sai#13 saddin[13]# an35 sai#14 saddin[14]# an31 saic# saddinclk# aj33 sao#0 saddout[0]# j1 sao#1 saddout[1]# j3 sao#2 saddout[2]# c7 sao#3 saddout[3]# a7 sao#4 saddout[4]# e5 sao#5 saddout[5]# a5 sao#6 saddout[6]# e7 sao#7 saddout[7]# c1 sao#8 saddout[8]# c5 table 23. pin name abbreviations (continued) abbreviation full name pin
58 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information sao#9 saddout[9]# c3 sao#10 saddout[10]# g1 sao#11 saddout[11]# e1 sao#12 saddout[12]# a3 sao#13 saddout[13]# g5 sao#14 saddout[14]# g3 saoc# saddoutclk# e3 scnck1 scanclk1 s1 scnck2 scanclk2 s5 scninv scaninteval s3 scnsn scanshiften q5 sd#0 sdata[0]# aa35 sd#1 sdata[1]# w37 sd#2 sdata[2]# w35 sd#3 sdata[3]# y35 sd#4 sdata[4]# u35 sd#5 sdata[5]# u33 sd#6 sdata[6]# s37 sd#7 sdata[7]# s33 sd#8 sdata[8]# aa33 sd#9 sdata[9]# ae37 sd#10 sdata[10]# ac33 sd#11 sdata[11]# ac37 sd#12 sdata[12]# y37 sd#13 sdata[13]# aa37 sd#14 sdata[14]# ac35 sd#15 sdata[15]# s35 sd#16 sdata[16]# q37 sd#17 sdata[17]# q35 sd#18 sdata[18]# n37 sd#19 sdata[19]# j33 sd#20 sdata[20]# g33 sd#21 sdata[21]# g37 sd#22 sdata[22]# e37 sd#23 sdata[23]# g35 sd#24 sdata[24]# q33 sd#25 sdata[25]# n33 sd#26 sdata[26]# l33 sd#27 sdata[27]# n35 table 23. pin name abbreviations (continued) abbreviation full name pin sd#28 sdata[28]# l37 sd#29 sdata[29]# j37 sd#30 sdata[30]# a37 sd#31 sdata[31]# e35 sd#32 sdata[32]# e31 sd#33 sdata[33]# e29 sd#34 sdata[34]# a27 sd#35 sdata[35]# a25 sd#36 sdata[36]# e21 sd#37 sdata[37]# c23 sd#38 sdata[38]# c27 sd#39 sdata[39]# a23 sd#40 sdata[40]# a35 sd#41 sdata[41]# c35 sd#42 sdata[42]# c33 sd#43 sdata[43]# c31 sd#44 sdata[44]# a29 sd#45 sdata[45]# c29 sd#46 sdata[46]# e23 sd#47 sdata[47]# c25 sd#48 sdata[48]# e17 sd#49 sdata[49]# e13 sd#50 sdata[50]# e11 sd#51 sdata[51]# c15 sd#52 sdata[52]# e9 sd#53 sdata[53]# a13 sd#54 sdata[54]# c9 sd#55 sdata[55]# a9 sd#56 sdata[56]# c21 sd#57 sdata[57]# a21 sd#58 sdata[58]# e19 sd#59 sdata[59]# c19 sd#60 sdata[60]# c17 sd#61 sdata[61]# a11 sd#62 sdata[62]# a17 sd#63 sdata[63]# a15 sdic#0 sdatainclk[0]# w33 sdic#1 sdatainclk[1]# j35 sdic#2 sdatainclk[2]# e27 table 23. pin name abbreviations (continued) abbreviation full name pin
chapter 11 pin descriptions 59 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information sdic#3 sdatainclk[3]# e15 sdinv# sdatainvalid# an33 sdoc#0 sdataoutclk[0]# ae35 sdoc#1 sdataoutclk[1]# c37 sdoc#2 sdataoutclk[2]# a33 sdoc#3 sdataoutclk[3]# c11 sdov# sdataoutvalid# al31 sfillv# sfillvalid# aj31 smi# an5 stpc# stpclk# ac1 tck q1 tdi u1 tdo u5 thda thermda s7 thdc thermdc u7 tms q3 trst# u3 vcc v cc_core b4 vcc v cc_core b8 vcc v cc_core b12 vcc v cc_core b16 vcc v cc_core b20 vcc v cc_core b24 vcc v cc_core b28 vcc v cc_core b32 vcc v cc_core b36 vcc v cc_core d2 vcc v cc_core d4 vcc v cc_core d8 vcc v cc_core d12 vcc v cc_core d16 vcc v cc_core d20 vcc v cc_core d24 vcc v cc_core d28 vcc v cc_core d32 vcc v cc_core f12 table 23. pin name abbreviations (continued) abbreviation full name pin vcc v cc_core f16 vcc v cc_core f20 vcc v cc_core f24 vcc v cc_core f28 vcc v cc_core f32 vcc v cc_core f34 vcc v cc_core f36 vcc v cc_core h2 vcc v cc_core h4 vcc v cc_core h12 vcc v cc_core h16 vcc v cc_core h20 vcc v cc_core h24 vcc v cc_core k32 vcc v cc_core k34 vcc v cc_core k36 vcc v cc_core m2 vcc v cc_core m4 vcc v cc_core m6 vcc v cc_core m8 vcc v cc_core p30 vcc v cc_core p32 vcc v cc_core p34 vcc v cc_core p36 vcc v cc_core r2 vcc v cc_core r4 vcc v cc_core r6 vcc v cc_core r8 vcc v cc_core t30 vcc v cc_core t32 vcc v cc_core t34 vcc v cc_core t36 vcc v cc_core v2 vcc v cc_core v4 table 23. pin name abbreviations (continued) abbreviation full name pin
60 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information vcc v cc_core v6 vcc v cc_core v8 vcc v cc_core x30 vcc v cc_core x32 vcc v cc_core x34 vcc v cc_core x36 vcc v cc_core z2 vcc v cc_core z4 vcc v cc_core z6 vcc v cc_core z8 vcc v cc_core ab30 vcc v cc_core ab32 vcc v cc_core ab34 vcc v cc_core ab36 vcc v cc_core ad2 vcc v cc_core ad4 vcc v cc_core ad6 vcc v cc_core af14 vcc v cc_core af18 vcc v cc_core af22 vcc v cc_core af26 vcc v cc_core af34 vcc v cc_core af36 vcc v cc_core ah2 vcc v cc_core ah4 vcc v cc_core ah10 vcc v cc_core ah14 vcc v cc_core ah18 vcc v cc_core ah22 vcc v cc_core ah26 vcc v cc_core ak10 vcc v cc_core ak14 vcc v cc_core ak18 vcc v cc_core ak22 table 23. pin name abbreviations (continued) abbreviation full name pin vcc v cc_core ak26 vcc v cc_core ak30 vcc v cc_core ak34 vcc v cc_core ak36 vcc v cc_core aj5 vcc v cc_core al5 vcc v cc_core am2 vcc v cc_core am10 vcc v cc_core am14 vcc v cc_core am18 vcc v cc_core am22 vcc v cc_core am26 vcc v cc_core am22 vcc v cc_core am26 vcc v cc_core am30 vcc v cc_core am34 vcca aj23 vid[0] l1 vid[1] l3 vid[2] l5 vid[3] l7 vid[4] j7 vref_s vref_sys w5 vss b2 vss b6 vss b10 vss b14 vss b18 vss b22 vss b26 vss b30 vss b34 vss d6 vss d10 vss d14 vss d18 table 23. pin name abbreviations (continued) abbreviation full name pin
chapter 11 pin descriptions 61 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information vss d22 vss d26 vss d30 vss d34 vss d36 vss f2 vss f4 vss f6 vss f10 vss f14 vss f18 vss f22 vss f26 vss h14 vss h18 vss h22 vss h26 vss h34 vss h36 vss k2 vss k4 vss k6 vss m30 vss m32 vss m34 vss m36 vss p2 vss p4 vss p6 vss p8 vss r30 vss r32 vss r34 vss r36 vss t2 vss t4 vss t6 vss t8 vss v30 table 23. pin name abbreviations (continued) abbreviation full name pin vss v32 vss v34 vss v36 vss x2 vss x4 vss x6 vss x8 vss z30 vss z32 vss z34 vss z36 vss ab2 vss ab8 vss ab4 vss ab6 vss ad32 vss ad34 vss ad36 vss af2 vss af4 vss af12 vss af16 vss ah12 vss ah16 vss ah20 vss ah24 vss ah28 vss ah32 vss ah34 vss ah36 vss ak2 vss ak4 vss ak12 vss ak16 vss ak20 vss ak24 vss ak28 vss ak32 vss am4 table 23. pin name abbreviations (continued) abbreviation full name pin
62 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information vss am6 vss am12 vss am16 vss am20 vss am24 vss am28 vss am32 vss am36 zn ac5 zp ae5 table 23. pin name abbreviations (continued) abbreviation full name pin
chapter 11 pin descriptions 63 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 11.2 pin list table 24 on page 64 cross-references socket a pin location to signal name. the ?l? (level) column shows the electrical specification for this pin. ?p? indicates a push-pull mode driven by a single source. ?o? indicates open-drain mode that allows devices to share the pin. note: the amd athlon processor supports push-pull drivers. for more information, see ?push-pull (pp) drivers? on page 6. the ?p? (port) column indicates if this signal is an input (i), output (o), or bidirectional (b) signal. the ?r? (reference) column indicates if this signal should be referenced to vss (g) or v cc_core (p) planes for the purpose of signal routing with respect to the current return paths.
64 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information table 24. cross-reference by pin location pin name description l p r a1 no pin page 75 - - - a3 saddout[12]# p o g a5 saddout[5]# p o g a7 saddout[3]# p o g a9 sdata[55]# p b p a11 sdata[61]# p b p a13 sdata[53]# p b g a15 sdata[63]# p b g a17 sdata[62]# p b g a19 nc pin page 75 - - - a21 sdata[57]# p b g a23 sdata[39]# p b g a25 sdata[35]# p b p a27 sdata[34]# p b p a29 sdata[44]# p b g a31 nc pin page 75 - - - a33 sdataoutclk[2]# p o p a35 sdata[40]# p b g a37 sdata[30]# p b p b2 vss --- b4 v cc_core --- b6 vss --- b8 v cc_core --- b10 vss --- b12 v cc_core --- b14 vss --- b16 v cc_core --- b18 vss --- b20 v cc_core --- b22 vss --- b24 v cc_core --- b26 vss --- b28 v cc_core --- b30 vss --- b32 v cc_core --- b34 vss --- b36 v cc_core --- c1 saddout[7]# p o g c3 saddout[9]# p o g c5 saddout[8]# p o g c7 saddout[2]# p o g c9 sdata[54]# p b p c11 sdataoutclk[3]# p o g c13 nc pin page 75 - - - c15 sdata[51]# p b p c17 sdata[60]# p b g c19 sdata[59]# p b g c21 sdata[56]# p b g c23 sdata[37]# p b p c25 sdata[47]# p b g c27 sdata[38]# p b g c29 sdata[45]# p b g c31 sdata[43]# p b g c33 sdata[42]# p b g c35 sdata[41]# p b g c37 sdataoutclk[1]# p o g d2 v cc_core --- d4 v cc_core --- d6 vss --- d8 v cc_core --- d10 vss --- d12 v cc_core --- d14 vss --- d16 v cc_core --- d18 vss --- d20 v cc_core --- table 24. cross-reference by pin location pin name description l p r
chapter 11 pin descriptions 65 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information d22vss --- d24 v cc_core --- d26vss --- d28 v cc_core --- d30vss --- d32 v cc_core --- d34vss --- d36vss --- e1 saddout[11]# p o p e3 saddoutclk# p o g e5 saddout[4]# p o p e7 saddout[6]# p o g e9 sdata[52]# p b p e11 sdata[50]# p b p e13 sdata[49]# p b g e15 sdatainclk[3]# p i g e17 sdata[48]# p b p e19 sdata[58]# p b g e21 sdata[36]# p b p e23 sdata[46]# p b p e25 nc pin page 75 - - - e27 sdatainclk[2]# p i g e29 sdata[33]# p b p e31 sdata[32]# p b p e33 nc pin page 75 - - - e35 sdata[31]# p b p e37 sdata[22]# p b g f2 vss --- f4 vss --- f6 vss --- f8 nc pin page 75 - - - f10 vss --- f12 v cc_core --- f14 vss --- table 24. cross-reference by pin location pin name description l p r f16 v cc_core --- f18 vss --- f20 v cc_core --- f22 vss --- f24 v cc_core --- f26 vss --- f28 v cc_core --- f30 nc pin page 75 - - - f32 v cc_core --- f34 v cc_core --- f36 v cc_core --- g1 saddout[10]# p o p g3 saddout[14]# p o g g5 saddout[13]# p o g g7 key pin page 75 - - - g9 key pin page 75 - - - g11 nc pin page 75 - - - g13 nc pin page 75 - - - g15 key pin page 75 - - - g17 key pin page 75 - - - g19 nc pin page 75 - - - g21 nc pin page 75 - - - g23 key pin page 75 - - - g25 key pin page 75 - - - g27 nc pin page 75 - - - g29 nc pin page 75 - - - g31 nc pin page 75 - - - g33 sdata[20]# p b g g35 sdata[23]# p b g g37 sdata[21]# p b g h2 v cc_core --- h4 v cc_core --- h6 nc pin page 75 - - - table 24. cross-reference by pin location pin name description l p r (continued)
66 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information h8 nc pin page 75 - - - h10 nc pin page 75 - - - h12 v cc_core --- h14 vss --- h16 v cc_core --- h18 vss --- h20 v cc_core --- h22vss --- h24 v cc_core --- h26vss --- h28 nc pin page 75 - - - h30 nc pin page 75 - - - h32 nc pin page 75 - - - h34vss --- h36vss --- j1 saddout[0]# page 76 p o - j3 saddout[1]# page 76 p o - j5 nc pin page 75 - - - j7 vid[4] page 76 o o - j31 nc pin page 75 - - - j33 sdata[19]# p b g j35 sdatainclk[1]# p i p j37 sdata[29]# p b p k2 vss --- k4 vss --- k6 vss --- k8 nc pin page 75 - - - k30 nc pin page 75 - - - k32 v cc_core --- k34 v cc_core --- k36 v cc_core --- l1 vid[0] page 76 o o - l3 vid[1] page 76 o o - table 24. cross-reference by pin location pin name description l p r l5 vid[2] page 76 o o - l7 vid[3] page 76 o o - l31 nc pin page 75 - - - l33 sdata[26]# p b p l35 nc pin page 75 - - - l37 sdata[28]# p b p m2 v cc_core --- m4 v cc_core --- m6 v cc_core --- m8 v cc_core --- m30vss --- m32vss --- m34vss --- m36vss --- n1 picclk page 71 o i - n3 picd#[0] page 71 o b - n5 picd#[1] page 71 o b - n7 key pin page 75 - - - n31 nc pin page 75 - - - n33 sdata[25]# p b p n35 sdata[27]# p b p n37 sdata[18]# p b g p2 vss --- p4 vss --- p6 vss --- p8 vss --- p30 v cc_core --- p32 v cc_core --- p34 v cc_core --- p36 v cc_core --- q1 tck page 74 p i - q3 tms page 74 p i - q5 scanshiften page 76 p i - table 24. cross-reference by pin location pin name description l p r (continued)
chapter 11 pin descriptions 67 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information q7 key pin page 75 - - - q31 nc pin page 75 - - - q33 sdata[24]# p b p q35 sdata[17]# p b g q37 sdata[16]# p b g r2 v cc_core --- r4 v cc_core --- r6 v cc_core --- r8 v cc_core --- r30 vss --- r32 vss --- r34 vss --- r36 vss --- s1 scanclk1 page 76 p i - s3 scaninteval page 76 p i - s5 scanclk2 page 76 p i - s7 thermda page 76 - - - s31 nc pin page 75 - - - s33 sdata[7]# p b g s35 sdata[15]# p b p s37 sdata[6]# p b g t2 vss --- t4 vss --- t6 vss --- t8 vss --- t30 v cc_core --- t32 v cc_core --- t34 v cc_core --- t36 v cc_core --- u1 tdi page 74 p i - u3 trst# page 74 p i - u5 tdo page 74 p o - u7 thermdc page 76 - - - table 24. cross-reference by pin location pin name description l p r u31 nc pin page 75 - - - u33 sdata[5]# p b g u35 sdata[4]# p b g u37 nc pin page 75 - - - v2 v cc_core --- v4 v cc_core --- v6 v cc_core --- v8 v cc_core --- v30 vss --- v32 vss --- v34 vss --- v36 vss --- w1 fid[0] page 73 o o - w3 fid[1] page 73 o o - w5 vrefsys page 77 p - - w7 nc pin page 75 - - - w31 nc pin page 75 - - - w33 sdatainclk[0]# p i g w35 sdata[2]# p b g w37 sdata[1]# p b p x2 vss --- x4 vss --- x6 vss --- x8 vss --- x30 v cc_core --- x32 v cc_core --- x34 v cc_core --- x36 v cc_core --- y1 fid[2] page 73 o o - y3 fid[3] page 73 o o - y5 nc pin page 75 - - - y7 key pin page 75 - - - y31 nc pin page 75 - - - table 24. cross-reference by pin location pin name description l p r (continued)
68 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information y33 nc pin page 75 - - - y35 sdata[3]# p b g y37 sdata[12]# p b p z2 v cc_core --- z4 v cc_core --- z6 v cc_core --- z8 v cc_core --- z30 vss --- z32 vss --- z34 vss --- z36 vss --- aa1 dbrdy page 72 p o - aa3 dbreq# page 72 p i - aa5nc --- aa7 key pin page 75 - - - aa31 nc pin page 75 - - - aa33 sdata[8]# p b p aa35 sdata[0]# p b g aa37 sdata[13]# p b g ab2vss --- ab4vss --- ab6vss --- ab8vss --- ab30 v cc_core --- ab32 v cc_core --- ab34 v cc_core --- ab36 v cc_core --- ac1 stpclk# page 76 p i - ac3 plltest# page 75 p i - ac5 zn page 77 p - - ac7nc --- ac31 nc pin page 75 - - - ac33 sdata[10]# p b p table 24. cross-reference by pin location pin name description l p r ac35 sdata[14]# p b g ac37 sdata[11]# p b g ad2 v cc_core --- ad4 v cc_core --- ad6 v cc_core --- ad8 nc pin page 75 - - - ad30 nc pin page 75 - - - ad32vss --- ad34vss --- ad36vss --- ae1 a20m# p i - ae3 pwrok p i - ae5 zp page 77 p - - ae7 nc --- ae31 nc pin page 75 - - - ae33 saddin[5]# p i g ae35 sdataoutclk[0]# p o p ae37 sdata[9]# p b g af2 vss --- af4 vss --- af6 nc pin page 75 - - - af8 nc pin page 75 - - - af10 nc pin page 75 - - - af12vss --- af14 v cc_core --- af16vss --- af18 v cc_core --- af20vss --- af22 v cc_core --- af24vss --- af26 v cc_core --- af28 nc pin page 75 - - - af30 nc pin page 75 - - - table 24. cross-reference by pin location pin name description l p r (continued)
chapter 11 pin descriptions 69 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information af32 nc pin page 75 - - - af34 v cc_core --- af36 v cc_core --- ag1 ferr page 72 p o - ag3 reset# - i - ag5 nc pin page 75 - - - ag7 key pin page 75 - - - ag9 key pin page 75 - - - ag11 corefb page 72 - - - ag13 corefb# page 72 - - - ag15 key pin page 75 - - - ag17 key pin page 75 - - - ag19 nc pin page 75 - - - ag21 nc pin page 75 - - - ag23 nc pin page 75 - - - ag25 nc pin page 75 - - - ag27 key pin page 75 - - - ag29 key pin page 75 - - - ag31 fsb_sense[0] page 74 - o g ag33 saddin[2]# p i g ag35 saddin[11]# p i g ag37 saddin[7]# p i p ah2 v cc_core --- ah4 v cc_core --- ah6 amd pin page 71 - - - ah8 nc pin page 75 - - - ah10 v cc_core --- ah12vss --- ah14 v cc_core --- ah16vss --- ah18 v cc_core --- ah20vss --- ah22 v cc_core --- table 24. cross-reference by pin location pin name description l p r ah24vss --- ah26 v cc_core --- ah28vss --- ah30 fsb_sense[1] page 74 - o g ah32vss --- ah34vss --- ah36vss --- aj1 ignne# page 74 p i - aj3 init# page 74 p i - aj5 v cc_core --- aj7 nc pin page 75 - - - aj9 nc pin page 75 - - - aj11 nc pin page 75 - - - aj13 analog page 71 - - - aj15 nc pin page 75 - - - aj17 nc pin page 75 - - - aj19 nc pin page 75 - - - aj21 clkfwdrst page 71 p i p aj23 vcca page 76 - - - aj25 pllbypass# page 75 p i - aj27 nc pin page 75 - - - aj29 saddin[0]# page 76 p i - aj31 sfillvalid# p i g aj33 saddinclk# p i g aj35 saddin[6]# p i p aj37 saddin[3]# p i g ak2 vss - - - ak4 vss - - - ak6 cpu_presence# page 72 - - - ak8 nc pin page 75 - - - ak10 v cc_core --- ak12 vss - - - ak14 v cc_core --- ak16 vss - - - table 24. cross-reference by pin location pin name description l p r (continued)
70 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information ak18 v cc_core --- ak20 vss - - - ak22 v cc_core --- ak24 vss - - - ak26 v cc_core --- ak28 vss - - - ak30 v cc_core --- ak32 vss - - - ak34 v cc_core --- ak36 v cc_core --- al1 intr page 74 p i - al3 flush# page 74 p i - al5 v cc_core --- al7 nc pin page 75 - - - al9 nc pin page 75 - - - al11 nc pin page 75 - - - al13 pllmon2 page 75 o o - al15 pllbypassclk# page 75 p i - al17 clkin# page 71 p i p al19 rstclk# page 71 p i p al21 k7clkout page 75 p o - al23 connect page 72 p i p al25 nc pin page 75 - - - al27 nc pin page 75 - - - al29 saddin[1]# page 76 p i - al31 sdataoutvalid# p o p al33 saddin[8]# p i p al35 saddin[4]# p i g al37 saddin[10]# p i g am2 v cc_core --- am4vss --- am6vss --- am8 nc pin page 75 - - - table 24. cross-reference by pin location pin name description l p r am10 v cc_core --- am12vss --- am14 v cc_core --- am16vss --- am18 v cc_core --- am20vss --- am22 v cc_core --- am24vss --- am26 v cc_core --- am28vss --- am30 v cc_core --- am32vss --- am34 v cc_core --- am36vss --- an1 no pin page 75 - - - an3 nmi p i - an5 smi# p i - an7 nc pin page 75 - - - an9 nc pin page 75 - - - an11 nc pin page 75 - - - an13 pllmon1 page 75 o b - an15 pllbypassclk page 75 p i - an17 clkin page 71 p i p an19 rstclk page 71 p i p an21 k7clkout# page 75 p o - an23 procrdy p o p an25 nc pin page 75 - - - an27 nc pin page 75 - - - an29 saddin[12]# p i g an31 saddin[14]# p i g an33 sdatainvalid# p i p an35 saddin[13]# p i g an37 saddin[9]# p i g table 24. cross-reference by pin location pin name description l p r (continued)
chapter 11 pin descriptions 71 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 11.3 detailed pin descriptions the information in this section pertains to table 24 on page 64. a20m# pin a20m# is an input from the system used to simulate address wrap-around in the 20-bit 8086. amd pin amd socket a processors do not implement a pin at location ah6. all socket a designs must have a top plate or cover that blocks this pin location. when the cover plate blocks this location, a non-amd part (e.g., pga370) does not fit into the socket. however, socket manufacturers are allowed to have a contact loaded in the ah6 posi tion. therefore, motherboard socket design should account fo r the possibility that a contact could be loaded in this position. amd athlon? system bus pins see the amd athlon? system bus specification , order# 21902 for information about the system bus pins?procrdy, pwrok, reset#, saddin[14:2]#, saddinclk#, saddout[14:2]#, saddoutclk#, sdata[63:0]#, sdatainclk[3:0]#, sdatainvalid#, sdataoutclk[3:0]#, sdataoutvalid#, sfillvalid#. analog pin treat this pin as a nc. apic pins, picclk, picd[1:0]# the advanced programmable interrupt controller (apic) is a feature that provides a flexible and expandable means of delivering interrupts in a system using an amd processor. the pins, picd[1:0], are the bi-dir ectional message-passing signals used for the apic and are driven to the southbridge or a dedicated i/o apic. the pin, picclk, must be driven with a valid clock input. for more information, see table 19, ?apic pin ac and dc characteristics,? on page 44. clkfwdrst pin clkfwdrst resets clock-forward circuitry for both the system and processor. clkin, rstclk (sysclk) pins connect clkin with rstclk and name it sysclk. connect clkin# with rstclk# and name it sysclk#. length match the clocks from the clock generator to the northbridge and processor. see ?sysclk and sysclk#? on page 76 for more information.
72 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information connect pin connect is an input from the system used for power management and clock-forward initialization at reset. corefb and corefb# pins corefb and corefb# are outputs to the system that provide processor core voltage feedback to the system. cpu_presence# pin cpu_presence# is connected to vss on the processor package. if pulled-up on the motherboard, cpu_presence# may be used to detect the presence or absence of a processor in the socket a-style socket. dbrdy and dbreq# pins dbrdy and dbreq# are routed to the debug connector. dbreq# is tied to v cc_core with a pullup resistor. ferr pin ferr is an output to the system that is asserted for any unmasked numerical exception independent of the ne bit in cr0. ferr is a push-pull active high signal that must be inverted and level shifted to an active low signal. for more information about ferr and ferr#, see the ?required circuits? chapter of the amd athlon? processor-based motherboard design guide , order# 24363.
chapter 11 pin descriptions 73 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information fid[3:0] pins fid[3] (y3), fid[2] (y1), fid[1] (w3), and fid[0] (w1) are the 4-bit processor clock-to-sysclk ratio. table 25 describes the encodings of the clock multipliers on fid[3:0]. the fid[3:0] signals are open-dra in processor outputs that are pulled high on the motherboard and sampled by the chipset to determine the sip (serialization initialization packet) that is sent to the processor. the fid[3:0] signals are valid after pwrok is asserted. the fid[3:0]signals must not be sampled until they become valid. see the amd athlon? system bus specification , order# 21902 for more information about serialization initialization packets and sip protocol. the processor fid[3:0] outputs are open-drain and 2.5 v tolerant. to prevent damage to the processor, if these signals are pulled high to above 2.5 v, they must be electrically isolated from the processor. for information about the fid[3:0] table 25. fid[3:0] clock multiplier encodings fid[3:0] 2 processor clock to sysclk frequency ratio 0000 11 0001 11.5 0010 12 0011 12.5 1 0100 5 0101 5.5 0110 6 0111 6.5 1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 10.5 notes: 1. all ratios greater than or equal to 12.5x have the same fid[3:0] code of 0011b, which causes the sip configuration for all ratios of 12.5x or greater to be the same. 2. bios initializes the clk_ctl msr during the post routine. this clk_ctl setting is used with all fid combinations and selects a halt disconnect divisor and a stop grant disconnect divisor. for more information, refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656.
74 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information isolation circuit, see the amd athlon? processor-based motherboard design guide , order# 24363. see ?frequency identification (fid[3:0])? on page 33 for the dc characteristics for fid[3:0]. fsb_sense[1:0] pins fsb_sense[1:0] pins are either open circuit (logic level of 1) or are pulled to ground (logic level of 0) on the processor package with a 1 k ? resistor. in conjunction with a circuit on the motherboard, these pins may be used to automatically detect the front side bus (fsb) setting of this processor. proper detection of the fsb setting requires the implementation of a pull-up resistor on the motherboard. refer to the amd athlon? processor-based motherboard design guide , order# 24363 and the technical note fsb_sense auto detection circuitry for desktop processors , order# tn26673 for more information. table 26 is the truth table to determine the fsb of desktop processors. the fsb_sense[1:0] pins are 3.3-v tolerant. flush# pin flush# must be tied to v cc_core with a pullup resistor. if a debug connector is implemented, flush# is routed to the debug connector. ignne# pin ignne# is an input from the system that tells the processor to ignore numeric errors. init# pin init# is an input from the system that resets the integer registers without affecting the floating-point registers or the internal caches. execution starts at 0_ffff_fff0h. intr pin intr is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. jtag pins tck, tms, tdi, trst#, and tdo are the jtag interface. connect these pins directly to the motherboard debug connector. pull tdi, tck, tms, and trst# up to v cc_core with pullup resistors. table 26. front side bus sense truth table fsb_sense[1] fsb_sense[0] bus frequency 1 0 reserved 11 133 mhz 0 1 166 mhz 0 0 reserved
chapter 11 pin descriptions 75 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information k7clkout and k7clkout# pins k7clkout and k7clkout# are each run for two to three inches and then terminated with a resistor pair: 100 ohms to v cc_core and 100 ohms to vss. the effective termination resistance and voltage are 50 ohms and v cc_core /2. key pins these 16 locations are for processor type keying for forwards and backwards compatibility (g7, g9, g15, g17, g23, g25, n7, q7, y7, aa7, ag7, ag9, ag15, ag17, ag27, and ag29). motherboard designers should treat key pins like nc (no connect) pins. a socket designer has the option of creating a top mold piece that allows pga key pins only where designated. however, sockets that populate all 16 key pins must be allowed, so the motherboard must always provide for pins at all key pin locations. see ?nc pins? for more information. nc pins the motherboard should provide a plated hole for an nc pin. the pin hole should not be electrically connected to anything. nmi pin nmi is an input from the system that causes a non-maskable interrupt. pga orientation pins no pin is present at pin locations a1 and an1. motherboard designers should not allow for a pga socket pin at these locations. for more information, see the amd athlon? processor-based motherboard design guide , order# 24363. pll bypass and test pins plltest#, pllbypass#, pllmon1, pllmon2, pllbypassclk, and pllbypassclk# are the pll bypass and test interface. this interface is tied disabled on the motherboard. all six pin signals are routed to the debug connector. all four processor inputs (plltest#, pllbypass#, pllmon1, and pllmon2) are tied to v cc_core with pullup resistors. pwrok pin the pwrok input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. for more information, chapter 9, ?signal and power-up requirements? on page 45.
76 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information saddin[1:0]# and saddout[1:0]# pins the amd athlon xp processor model 8 does not support saddin[1:0]# or saddout[1:0]#. saddin[1]# is tied to vcc with pullup resistors, if this bit is not supported by the northbridge (future models can support saddin[1]#). saddout[1:0]# are tied to vcc with pullup resistors if these pins are supported by the northbridge. for more information, see the amd athlon? system bus specification , order# 21902. scan pins scanshiften, scanclk1, scaninteval, and scanclk2 are the scan interface. this interface is amd internal and is tied disabled with pulldown resistors to ground on the motherboard. smi# pin smi# is an input that causes the processor to enter the system management mode. stpclk# pin stpclk# is an input that causes the processor to enter a lower power mode and issue a stop grant special cycle. sysclk and sysclk# sysclk and sysclk# are differential input clock signals provided to the pll of the processor from a system-clock generator. see ?clkin, rstclk (sysclk) pins? on page 71 for more information. thermda and thermdc pins thermal diode anode and cathode pins are used to monitor the actual temperature of the processor die, providing more accurate temperature control to the system. see table 17, ?thermal diode electrical characteristics,? on page 42 for more information. vcca pin vcca is the processor pll supply. for information about the vcca pin, see table 5, ?vcca ac and dc characteristics,? on page 35 and the amd athlon? processor-based motherboard design guide , order# 24363. vid[4:0] pins the vid[4:0] (voltage identification) outputs are used to dictate the v cc_core voltage level. the vid[4:0] pins are strapped to ground or left unconnected on the processor package. the vid[4:0] pins are pulled-up on the motherboard and used by the v cc_core dc/dc converter. for more information, see table 27, ?vid[4:0] code to voltage definition,? on page 77.
chapter 11 pin descriptions 77 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information for more information, see the ?required circuits? chapter of the amd athlon? processor-based motherboard design guide , order# 24363. vrefsys pin vrefsys (w5) drives the threshold voltage for the system bus input receivers. the value of vrefsys is system specific. in addition, to minimize v cc_core noise rejection from vrefsys, include decoupling capacitors. for more information, see the amd athlon? processor-based motherboard design guide , order# 24363. zn and zp pins zn (ac5) and zp (ae5) are the push-pull compensation circuit pins. in push-pull mode (selected by the sip parameter syspushpull asserted), zn is tied to v cc_core with a resistor that has a resistance matching the impedance z 0 of the transmission line. zp is tied to vss with a resistor that has a resistance matching the impedance z 0 of the transmission line. table 27. vid[4:0] code to voltage definition vid[4:0] v cc_core (v) vid[4:0] v cc_core (v) 00000 1.850 10000 1.450 00001 1.825 10001 1.425 00010 1.800 10010 1.400 00011 1.775 10011 1.375 00100 1.750 10100 1.350 00101 1.725 10101 1.325 00111 1.675 10111 1.275 01000 1.650 11000 1.250 01001 1.625 11001 1.225 01010 1.600 11010 1.200 01011 1.575 11011 1.175 01100 1.550 11100 1.150 01101 1.525 11101 1.125 01110 1.500 11110 1.100 01111 1.475 11111 no cpu
78 pin descriptions chapter 11 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
chapter 12 ordering information 77 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information 12 ordering information this section provides the ordering information for the amd athlon? xp processor model 8. standard amd athlon? xp processor model 8 products amd standard products are available in several operating ranges. the ordering part numbers (opn) are formed by a combination of the elements, as shown in figure 17. figure 17. opn example for the amd athlon? xp processor model 8 d k v 3 opn 1 advanced front-side bus (fsb): c = 266, d = 333 size of l2 cache: 3 = 256 kbytes die temperature: t = 90c, v = 85c operating voltage: l = 1.50 v, u = 1.60 v, k = 1.65 v package type: d = opga model number: 1700 operates at 1467 mhz 2 , 1800 at 1533 mhz 2 , 1900 at 1600 mhz 2 , 2000 at 1667 mhz 2 , 2100 at 1733 mhz 2 , 2200 at 1800 mhz 2 , 2400 at 2000 mhz 2 , 2600 at 2083 mhz 3 or 2133 mhz 2 , 2700 at 2167 mhz 3 maximum power: a = desktop processor architecture segment: axd = amd athlon? xp processor model 8 with quantispeed? architecture for desktop products axd a d 2700 notes: 1. spaces are added to the number shown above for viewing clarity only. 2. this processor is available only with a 266 advanced fsb. 3. this processor is available only with a 333 advanced fsb.
78 ordering information chapter 12 amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information appendix a - thermal diode calculations 79 preliminary information appendix a thermal diode calculations this section contains information about the calculations for the on-die thermal diode of the amd athlon? xp processor model 8. for electrical information about this thermal diode, see table 17, ?thermal diode electrical characteristics,? on page 42. ideal diode equation the ideal diode equation uses the variables and constants defined in table 28. table 28. constants and variables for the ideal diode equation equation symbol variable, constant description n f, lumped lumped ideality factor k boltzmann constant q electron charge constant t diode temperature (kelvin) v be voltage from base to emitter i c collector current i s saturation current
80 appendix a - thermal diode calculations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information equation (1) shows the ideal diode calculation. sourcing two currents and using equation (1) derives the difference in the base-to-emitter voltage that leads to finding the diode temperature as shown in equation (2). the use of dual sourcing currents allows the measurement of the thermal diode temperature to be more accurate and less susceptible to die and process revisions. temperature sensors that utilize series resistance cancellation can use more than two sourcing currents and are suitable to be used with the amd thermal diode. equation (2) is the formula for calculating the temperature of a thermal diode. temperature offset correction a temperature offset may be required to correct the value measured by a temperature sensor. an offset is necessary if a difference exists between the lumped ideality factor of the processor and the ideality factor assumed by the temperature sensor. the lumped ideality factor can be calculated using the equations in this section to find the temperature offset that should be used with the temperature sensor. table 29 shows the constants and variables used to calculate the temperature offset correction. (1) v be n flumped , k q -- - t i c i s --- - ?? ?? ln ??? = (2) t v be high , v be low , ? n flumped , k q -- - i high i low ------- - ?? ?? ln ?? -------------------------------------------------------------- - = table 29. constants and variables used in temperature offset equations equation symbol variable, constant description n f, actual actual ideality factor n f, lumped lumped ideality factor n f, ts ideality factor assumed by temperature sensor i high high sourcing current i low low sourcing current t die, spec die temperature specification t offset temperature offset
appendix a - thermal diode calculations 81 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information the formulas in equation (3) and equation (4) can be used to calculate the temperature offset for temperature sensors that do not employ series resistance cancellation. the result is added to the value measured by the temperature sensor. contact the vendor of the temperature sensor being used for the value of n f,ts . refer to the document, on-die thermal diode characterization , order# 25443, for further details. equation (3) shows the equation for calculating the lumped ideality factor (n f, lumped ) in sensors that do not employ series resistance cancellation. equation (4) shows the equation for calculating temperature offset (t offset ) in sensors that do not employ series resistance cancellation. equation (5) is the temperature offset for temperature sensors that utilize series resistance cancellation. add the result to the value measured by the temperature sensor. note that the value of n f,ts in equation (5) may not equal the value used in equation (4). (3) n flumped , n factual , = r t i high i low ? () ? k q -- - t die spec , 273.15 + () i high i low ------- - ?? ?? ln ? ---------------------------------------------------------------------- + (4) t offset t die spec , 273.15 + () =1 n flumped , n fts , --------------- ? ?? ?? ? (5) t offset t die spec , 273.15 + () =1 n f actual , n fts , --------------- ? ?? ?? ?
82 appendix a - thermal diode calculations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information
25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information appendix b - conventions and abbreviations 83 appendix b conventions and abbreviations this section contains information about the conventions and abbreviations used in this document. signals and bits active-low signals?signal names containing a pound sign, such as sfill#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. when used in this context, high and low are written with an initial upper case letter. signal ranges?in a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, d[63:0]). reserved bits and signals?signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. these bits and signals are reserved by amd for future implementations. when software reads registers with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. three-state?in timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels.
84 appendix b - conventions and abbreviations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information invalid and don?t-care?in timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. data terminology the following list defines data terminology: quantities a word is two bytes (16 bits) a doubleword is four bytes (32 bits) a quadword is eight bytes (64 bits) addressing?memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. abbreviations? the following notation is used for bits and bytes: kilo (k, as in 4-kbyte page) mega (m, as in 4 mbits/sec) giga (g, as in 4 gbytes of memory space) see table 30 on page 85 for more abbreviations. little-endian convention?the byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left?the little end is on the right and the big end is on the left. data structure diagrams in memory show low addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. bit ranges?in text, bit ranges are shown with a dash (for example, bits 9?1). when accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, ad[31:0]). bit values?bits can either be set to 1 or cleared to 0. hexadecimal and binary numbers?unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b.
appendix b - conventions and abbreviations 85 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information abbreviations and acronyms table 30 contains the definitions of abbreviations used in this document. table 30. abbreviations abbreviation meaning aampere f farad g giga- gbit gigabit gbyte gigabyte ghz gigahertz hhenry h hexadecimal kkilo- kbyte kilobyte lbf foot-pound m mega- mbit megabit mbyte megabyte mhz megahertz m milli- ms millisecond mw milliwatt micro- a microampere fmicrofarad h microhenry s microsecond v microvolt n nano- na nanoampere nf nanofarad nh nanohenry ns nanosecond ohm ohm
86 appendix b - conventions and abbreviations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information table 31 contains the definitions of acronyms used in this document. ppico- pa picoampere pf picofarad ph picohenry ps picosecond s second vvolt wwatt table 31. acronyms abbreviation meaning acpi advanced configuration and power interface agp accelerated graphics port apci agp peripheral component interconnect api application programming interface apic advanced programmable interrupt controller bios basic input/output system bist built-in self-test biu bus interface unit cpga ceramic pin grid array ddr double-data rate dimm dual inline memory module dma direct memory access dram direct random access memory dsp digital signal processing eide enhanced integrated device electronics eisa extended industry standard architecture eprom enhanced programmable read only memory fifo first in, first out gart graphics address remapping table hstl high-speed transistor logic table 30. abbreviations (continued) abbreviation meaning
appendix b - conventions and abbreviations 87 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information ide integrated device electronics isa industry standard architecture ipc instructions per cycle jedec joint electron device engineering council jtag joint test action group lan large area network lru least-recently used lvttl low voltage transistor transistor logic msb most significant bit mtrr memory type and range registers mux multiplexer nmi non-maskable interrupt od open-drain opga organic pin grid array pa physical address pbga plastic ball grid array pci peripheral component interconnect pde page directory entry pdt page directory table pga pin grid array pll phase locked loop pmsm power management state machine pos power-on suspend post power-on self-test pp push-pull ram random access memory rom read only memory rxa read acknowledge queue scsi small computer system interface sdi system dram interface sdram synchronous direct random access memory simd single instruction multiple data sip serial initialization packet smbus system management bus table 31. acronyms (continued) abbreviation meaning
88 appendix b - conventions and abbreviations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information spd serial presence detect sram synchronous random access memory srom serial read only memory tlb translation lookaside buffer tom top of memory ttl transistor transistor logic vas virtual address space vpa virtual page address vga video graphics adapter usb universal serial bus zdb zero delay buffer table 31. acronyms (continued) abbreviation meaning
appendix b - conventions and abbreviations 89 25175e?november 2002 amd athlon? xp processor model 8 data sheet preliminary information related publications these documents provide helpful information about the amd athlon? xp processor model 8, and can be found with other related documents at the amd web site, http://www.amd.com . amd athlon? processor x86 code optimization guide, order# 22007 amd processor recognition application note, order# 20734 methodologies for measuring temperature on amd athlon? and amd duron? processors, order# 24228 amd thermal, mechanical, and chassis cooling design guide , order# 23794 builders guide for desktop/tower systems , order# 26003 other web sites of interest include the following: jedec home page?www.jedec.org ieee home page? www.computer.org agp forum?www.agpforum.or
90 appendix b - conventions and abbreviations amd athlon? xp processor model 8 data sheet 25175e?november 2002 preliminary information

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